Improved Quantum Dot Cellular Automata 4:1 Multiplexer Circuit Unit

2014 ◽  
Vol 2014 (1) ◽  
pp. 37-44 ◽  
Author(s):  
Arighna Sarkar ◽  
◽  
Debarka Mukhopadhyay ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

A Novel Enhanced-Majority-Voter Universal Gate in Quantum Dot Cellular Automata with Energy Dissipation Analysis

2017 ◽  
Vol 9 (3) ◽  
pp. 03034-1-03034-7 ◽  
Author(s):  
S. Umira ◽  
◽  
R. Qadri ◽  
Z. A. Bangi ◽  
M. Tariq Banday ◽  
...  
Keyword(s):  
Energy Dissipation ◽  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata ◽  
Majority Voter ◽  
Universal Gate

Design of Novel Efficient Multiplexer Architecture for Quantum-dot Cellular Automata

2017 ◽  
Vol 9 (1) ◽  
pp. 01012-1-01012-7 ◽  
Author(s):  
Hamid Rashidi ◽  
◽  
Abdalhossein Rezai ◽  
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

An efficient, scalable, regular clocking scheme based on quantum dot cellular automata

2021 ◽  
Author(s):  
Jayanta Pal ◽  
Amit Kumar Pramanik ◽  
Jyotirmoy Sil Sharma ◽  
Apu Kumar Saha ◽  
Bibhash Sen
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Quantum Dot Cellular Automata

Hamming Code Generators using LTEx Module of Quantum-dot Cellular Automata

2019 ◽  
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Bansibadan Maji ◽  
Asish Kumar Mukhopadhyay
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Hamming Code ◽  
Quantum Dot Cellular Automata ◽  
Code Generators
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