Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

2020 ◽  
Vol 12 ◽  
Author(s):  
Arindam Sadhu ◽  
Rimpa Dey Sarkar ◽  
Kunal Das ◽  
Debashis De ◽  
Maitreyi Ray Kanjilal

Aims: Embedded system plays a vital role in today’s life. Hence our motivation is concentrated on area-delay-energy efficient embedded system design in post-CMOS technology i.e. QCA. Objectives: The research is focused on area-delay-energy efficient configurable logic block (CLB) design for field programmable gate array architecture (FPGA) with successful simulation based on a next generation technology, Quantum-dot cellular automata. Methodology: Each proposed circuits are designed in post CMOS 4 dot 2 electron technology i.e. QCA(Quantum Dot Cellular Automata) which has been adopted in circuit implementation due to Low power dissipation, high clock frequency and high package density. Functionality of every circuit is verified by QCADesigner. QCAPro tool is used for power dissipation measurement. Results: In contrast a new approach of using de-multiplexer replacing the decoder has been introduced which results in reduction of the average energy dissipation almost 57%. A NOR based D flip-flop memory architecture and multiplexer is also used in the look up table for the configurable logic block. The proposed architecture thus reduces the overall latency. Proposed CLB is consists of 6356 number of QCA cell with covering 7.44 um2 area. Write and read latency of proposed CLB is 12 and 7.25 QCA clock respectively. Conclusion: The presented paper concludes those read and write latency reduction occurs; average energy dissipation, leakage and switching energy dissipation has been reduced massively and ensues an advantage of overall reduction of the latency for the proposed CLB in the process.


2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.


2020 ◽  
Vol 18 (06) ◽  
pp. 2050032
Author(s):  
Suhaib Ahmed ◽  
Syed Farah Naz

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.


2019 ◽  
Vol 8 (2S11) ◽  
pp. 2707-2716

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells


2015 ◽  
Vol 24 (10) ◽  
pp. 1550153 ◽  
Author(s):  
Shaahin Angizi ◽  
Samira Sayedsalehi ◽  
Arman Roohi ◽  
Nader Bagherzadeh ◽  
Keivan Navi

Quantum-dot Cellular Automata (QCA) is an attractive nanoelectronics paradigm which is widely advocated as a possible replacement of conventional CMOS technology. Designing memory cells is a very interesting field of research in QCA domain. In this paper, we are going to propose novel nanotechnology-compatible designs based on the majority gate structures. In the first step, this objective is accomplished by QCA implementation of two well-organized JK flip-flop designs and in the second step; synchronous counters with different sizes are presented as an application. To evaluate functional correctness of the proposed designs and compare with state-of-the-art, QCADesigner tool is employed.


2018 ◽  
Vol 27 (10) ◽  
pp. 1830005 ◽  
Author(s):  
Mahya Rahimpour Gadim ◽  
Nima Jafari Navimipour

Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in the field of ALU design. This paper provides the comprehensive, systematic and detailed study and survey of the state-of-the-art techniques and mechanisms in the field of QCA-based ALU designing. There are three categories in which QCA plays a role: ALU, logic unit (LU) and arithmetic unit (AU). Each category presents the important studies. In addition, this paper reviews the major developments in these three categories and it plans the new challenges. Furthermore, it provides the identification of open issues and guidelines for future research. Also, a Systematic Literature Review (SLR) on QCA-based ALU, LU and AU is discussed in this paper. We identified 1,960 papers, which are reduced to 26 primary studies through our paper selection process. According to the obtained results from 2001 to 2015, the number of published articles are very high in 2014 and low in 2005 and 2009. This survey paper also provides a discussion of considered mechanisms in terms of ALU, LU and AU attribute as well as directions for future research.


2017 ◽  
Vol 7 ◽  
pp. 3543-3551 ◽  
Author(s):  
Milad Bagherian Khosroshahy ◽  
Mohammad Hossein Moaiyeri ◽  
Keivan Navi ◽  
Nader Bagherzadeh

2018 ◽  
Vol 57 (11) ◽  
pp. 3419-3428 ◽  
Author(s):  
Ali Newaz Bahar ◽  
Radhouane Laajimi ◽  
Md. Abdullah-Al-Shafi ◽  
Kawsar Ahmed

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