Concurrent Algorithm and Hardware Implementation for Low-Latency Turbo Decoder Using a Single MAP Decoder

2010 ◽  
Vol E93-B (1) ◽  
pp. 1-8
Author(s):  
Ya-Cheng LU ◽  
Erl-Huei LU
Keyword(s):  
Hardware Implementation ◽  
Low Latency ◽  
Turbo Decoder ◽  
Concurrent Algorithm ◽  
Map Decoder

scholarly journals Orthros: A Low-Latency PRF

2021 ◽  
pp. 37-77
Author(s):  
Subhadeep Banik ◽  
Takanori Isobe ◽  
Fukang Liu ◽  
Kazuhiko Minematsu ◽  
Kosei Sakamoto
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
State Of The Art ◽  
Security Analysis ◽  
Parallel Structure ◽  
Low Latency ◽  
Round Function ◽  
Minimum Latency ◽  
Primary Focus ◽  
Pseudorandom Function

We present Orthros, a 128-bit block pseudorandom function. It is designed with primary focus on latency of fully unrolled circuits. For this purpose, we adopt a parallel structure comprising two keyed permutations. The round function of each permutation is similar to Midori, a low-energy block cipher, however we thoroughly revise it to reduce latency, and introduce different rounds to significantly improve cryptographic strength in a small number of rounds. We provide a comprehensive, dedicated security analysis. For hardware implementation, Orthros achieves the lowest latency among the state-of-the-art low-latency primitives. For example, using the STM 90nm library, Orthros achieves a minimum latency of around 2.4 ns, while other constructions like PRINCE, Midori-128 and QARMA9-128- σ0 achieve 2.56 ns, 4.10 ns, 4.38 ns respectively.

Parallel turbo decoder using a low-latency Max-Log-MAP kernel for a VLIW DSP

2001 ◽  
Author(s):  
Yingtao Jiang ◽  
Jun Ma ◽  
Ali Saidi ◽  
Yuke Wang
Keyword(s):  
Low Latency ◽  
Turbo Decoder ◽  
Vliw Dsp ◽  
Log Map
Sign in / Sign up

Export Citation Format

Share Document