Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation

2010 ◽  
Vol E93-A (12) ◽  
pp. 2399-2408 ◽  
Author(s):  
Takashi ENAMI ◽  
Shinyu NINOMIYA ◽  
Ken-ichi SHINKAI ◽  
Shinya ABE ◽  
Masanori HASHIMOTO
Keyword(s):  
Power Supply ◽  
Process Variation ◽  
Timing Analysis ◽  
Power Supply Noise ◽  
Clock Jitter ◽  
Statistical Timing Analysis ◽  
Supply Noise ◽  
Statistical Timing

Research on Timing of on-Chip Power Supply Noise with Analysis of Scientific Data Materials

2013 ◽  
Vol 310 ◽  
pp. 494-497
Author(s):  
Xiao Guang Li
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Timing Analysis ◽  
Logic Gates ◽  
Scientific Data ◽  
New Method ◽  
Power Supply Noise ◽  
Supply Noise ◽  
On Chip

Aiming at the problems of the influence in power-supply variations on timing analysis, this paper presents a new method to assign a supply-dependent hold margin based on analysis of scientific data materials, which describe a method to accurately characterize logic gates for the sensitivity of delay on supply-voltage variations, and then the method use a commercial microcontroller as a design example. Experiment results shows that the new method with analysis of scientific materials can get a good performance, even under the existing noise.

Sign in / Sign up

Export Citation Format

Share Document