Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
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Published By IEEE Comput. Soc

0769505252

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Crosstalk aware static timing analysis: a two step approach

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838935 ◽

2002 ◽

Cited By ~ 16

Author(s):

B. Franzini ◽

C. Forzan ◽

D. Pandini ◽

P. Scandolara ◽

A. Dal Fabbro

Keyword(s):

Timing Analysis ◽

Static Timing Analysis ◽

Static Timing

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Power bus maximum voltage drop in digital VLSI circuits

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838881 ◽

2002 ◽

Cited By ~ 6

Author(s):

G. Bai ◽

S. Bobba ◽

I.N. Hajj

Keyword(s):

Voltage Drop ◽

Vlsi Circuits ◽

Digital Vlsi ◽

Power Bus ◽

Maximum Voltage

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LEMINGS: LSI's EMI-noise analysis with gate level simulator

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838865 ◽

2002 ◽

Cited By ~ 11

Author(s):

K. Shimazaki ◽

H. Tsujikawa ◽

S. Kojima ◽

S. Hirano

Keyword(s):

Noise Analysis

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On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838872 ◽

2002 ◽

Cited By ~ 1

Author(s):

Zhanping Chen ◽

Liqiong Wei ◽

Kaushik Roy

Keyword(s):

Low Voltage ◽

Cmos Circuits ◽

Control Techniques ◽

Leakage Control

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A reconfigurable low-power high-performance matrix multiplier design

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838891 ◽

2002 ◽

Cited By ~ 8

Author(s):

R. Lin

Keyword(s):

Low Power ◽

High Performance ◽

Performance Matrix

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ESD: design for IC chip quality and reliability

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838880 ◽

2002 ◽

Cited By ~ 6

Author(s):

C. Duvvury

Keyword(s):

Chip Quality ◽

Quality And Reliability

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Achieving the quality of verification for behavioral models with minimum effort

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838877 ◽

2002 ◽

Cited By ~ 8

Author(s):

T. Chen ◽

A. Von Mayrhauser ◽

M. Sahinoglu ◽

A. Hajjar ◽

C. Anderson

Keyword(s):

Behavioral Models

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Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838922 ◽

2002 ◽

Cited By ~ 2

Author(s):

V. Axelrad ◽

N. Cobb ◽

M. O'Brien ◽

V. Boksha ◽

T. Do ◽

...

Keyword(s):

Yield Analysis ◽

Analysis Methodology

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A proposal for accurately modeling frequency-dependent on-chip interconnect impedance

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838899 ◽

2002 ◽

Cited By ~ 1

Author(s):

Li-Fu Chang ◽

Keh-Jeng Dhang ◽

C. Bianchi

Keyword(s):

Frequency Dependent ◽

On Chip ◽

Interconnect Impedance

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Efficient hierarchical approach to test generation for digital systems

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525) ◽

10.1109/isqed.2000.838873 ◽

2002 ◽

Author(s):

R. Ubar ◽

J. Raik

Keyword(s):

Test Generation ◽

Digital Systems ◽

Hierarchical Approach

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Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc

Crosstalk aware static timing analysis: a two step approach

Power bus maximum voltage drop in digital VLSI circuits

LEMINGS: LSI's EMI-noise analysis with gate level simulator

On effective I/sub DDQ/ testing of low voltage CMOS circuits using leakage control techniques

A reconfigurable low-power high-performance matrix multiplier design

ESD: design for IC chip quality and reliability

Achieving the quality of verification for behavioral models with minimum effort

Efficient full-chip yield analysis methodology for OPC-corrected VLSI designs

A proposal for accurately modeling frequency-dependent on-chip interconnect impedance

Efficient hierarchical approach to test generation for digital systems

Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525)
Latest Publications