scholarly journals Realization of Efficient Multiplier for Low Power Biomedical Signal Processing System-on-Chip Design for Portable ECG Monitoring Systems

2015 ◽  
Vol 8 (24) ◽  
Author(s):  
R. Praveena ◽  
S. Nirmala
Keyword(s):  
Signal Processing ◽  
Processing System ◽  
System On Chip ◽  
Biomedical Signal Processing ◽  
Monitoring Systems ◽  
Ecg Monitoring ◽  
Signal Processing System ◽  
Chip Design ◽  
Biomedical Signal ◽  
On Chip

scholarly journals Signal processing system-on-chip design for biomedical applications

2017 ◽  
Vol 14 (24) ◽  
pp. 20171089-20171089 ◽  
Author(s):  
Song Ma ◽  
Liubin Li ◽  
Guan Wang ◽  
Yuhua Cheng
Keyword(s):  
Signal Processing ◽  
Biomedical Applications ◽  
Processing System ◽  
System On Chip ◽  
Signal Processing System ◽  
Chip Design ◽  
On Chip

An Ultra Low Energy Biomedical Signal Processing System Operating at Near-Threshold

2011 ◽  
Vol 5 (6) ◽  
pp. 546-554 ◽  
Author(s):  
Jos Hulzink ◽  
Mario Konijnenburg ◽  
Maryam Ashouei ◽  
Arjan Breeschoten ◽  
Torfinn Berset ◽  
...  
Keyword(s):  
Signal Processing ◽  
Processing System ◽  
Low Energy ◽  
Biomedical Signal Processing ◽  
Signal Processing System ◽  
Biomedical Signal ◽  
System Operating ◽  
Near Threshold

System on Chip Design for Multi-Principle of Relay Protection in the FPGA

2014 ◽  
Vol 668-669 ◽  
pp. 857-861
Author(s):  
Peng Fei Hu ◽  
Yu Xiang Yuan ◽  
Zhi Juan Qu ◽  
Xue Ping Jiang
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Relay Protection ◽  
Digital Signal ◽  
System On Chip ◽  
Process Scheduling ◽  
Chip Design ◽  
Protection Devices ◽  
On Chip ◽  
Set Up

To improve the reliability and integration of relay protection devices in power, the system on chip design for multi-principle of relay protection on FPGA is proposed. The data acquisition, digital signal processing, hardware protection algorithm, FPGA and MCU process scheduling, MCU and peripheral devices communication are designed, the hardware compilation model is set up by QuartusII on FPGA, and the simulation and experimental verification are performed. The results show that the proposed system can improve the speed of hardware protection and reduce the volume of the device, and has reconstruction on architecture.

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