scholarly journals Performance Evaluation of Encryption/Decryption Mechanisms to Enhance Data Security

2016 ◽  
Vol 9 (20) ◽  
Author(s):  
Narander Kumar ◽  
Priyanka Chaudhary
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Encryption Decryption

scholarly journals Modified Key Using Multi-Cycle Key In Vigenere Cipher

2019 ◽  
Vol 8 (2S11) ◽  
pp. 2600-2606 ◽  
Keyword(s):  
Data Security ◽  
Text Data ◽  
The Future ◽  
Encryption Decryption

Encryption-Decryption is one form of securing text data, images and sound in order to minimize data stealing, attack, etc. The purpose of this study is to modified encryption-decryption keys of Vigenere cipher.Based on experiment show that multi-cycle keyencryption-decryption have been implemented. Meanwhile, the best MAE values of final encryption process of 56.837 and final decryption process of 0. In other words, the modification of key is more efficient and effective for data security. Furthermore, the multi-cycle key encryption-decryption optimizing using metaheuristics as one of the future works that can be conducted in order to investigate the best encryption-decryption especially using Vigenere cipher.

scholarly journals DES encryption and decryption algorithm implementation based on FPGA

2020 ◽  
Vol 18 (2) ◽  
pp. 774
Author(s):  
Subhi R. M. Zeebaree
Keyword(s):  
Data Security ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
The Internet ◽  
Clock Frequency ◽  
Hardware Implementations ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Algorithm Implementation

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

scholarly journals IMPLEMENTASI KRIPTOGRAFI RSA DENGAN PHP

2017 ◽  
Vol 1 (1) ◽  
pp. 1
Author(s):  
Muhammad Yasin Simargolang
Keyword(s):  
Programming Language ◽  
Data Security ◽  
Art And Science ◽  
Encrypted Data ◽  
Rsa Algorithm ◽  
Private Key ◽  
Large Numbers ◽  
Encryption Decryption ◽  
Encryption Method ◽  
Data Transforming

Abstract - Cryptography is an art and science to maintain data security. In maintaining the security of cryptographic data transforming clear data (plaintext) into a password (ciphertext) that cannot be recognized. This ciphertext is then sent by the sender to the recipient. After arriving at the recipient, the ciphertext is transformed back into a plaintext form so that it can be recognized. The method used is the encryption method asymmetrical Rivest Shamir Adleman (RSA). The security of the RSA algorithm lies in the difficulty of factoring large numbers into prime factors. Factoring is done to obtain a private key. Making this application using the PHP programming language. The final result is a desktop-based application that can be used to encrypt text files. This application can be used as a way to secure data, because only authorized people can view encrypted data. Keywords - Cryptography, RSA, Encryption - Decryption, Text, PHP

scholarly journals Study of Data Security Algorithms using Verilog HDL

2015 ◽  
Vol 5 (5) ◽  
pp. 1092
Author(s):  
M. Sumathi ◽  
D. Nirmala ◽  
R. Immanuel Rajkumar
Keyword(s):  
Performance Evaluation ◽  
Data Security ◽  
Hardware Description Language ◽  
Performance Study ◽  
Verilog Hdl ◽  
Description Language ◽  
Quartus Ii ◽  
Encryption And Decryption ◽  
Different Types ◽  
Hardware Description

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim.

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