scholarly journals DES encryption and decryption algorithm implementation based on FPGA

2020 ◽  
Vol 18 (2) ◽  
pp. 774
Author(s):  
Subhi R. M. Zeebaree
Keyword(s):  
Data Security ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
The Internet ◽  
Clock Frequency ◽  
Hardware Implementations ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Algorithm Implementation

Nowadays there is a lot of importance given to data security on the internet. The DES is one of the most preferred block cipher encryption/decryption procedures used at present. This paper presents a high throughput reconfigurable hardware implementation of DES Encryption algorithm. This achieved by using a new proposed implementation of the DES algorithm using pipelined concept.  The implementation of the proposed design is presented by using Spartan-3E (XC3S500E) family FPGAs and is one of the fastest hardware implementations with much greater security. At a clock frequency of 167.448MHz for encryption and 167.870MHz for decryption, it can encrypt or decrypt data blocks at a rate of 10688Mbps.

AN FPGA IMPLEMENTATION OF THE GPRS ENCRYPTION ALGORITHM 3 (GEA3)

2005 ◽  
Vol 14 (02) ◽  
pp. 217-231 ◽  
Author(s):  
P. KITSOS ◽  
M. D. GALANIS ◽  
O. KOUFOPAVLOU
Keyword(s):  
Hardware Implementation ◽  
Block Cipher ◽  
Data Encryption ◽  
Encryption Algorithm ◽  
General Packet Radio Service ◽  
Silicon Area ◽  
Double Edge ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Significant Performance

The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

scholarly journals Study A Public Key in RSA Algorithm

2020 ◽  
Vol 5 (4) ◽  
pp. 395-398
Author(s):  
Taleb Samad Obaid
Keyword(s):  
Private Information ◽  
Original Data ◽  
Prime Numbers ◽  
Public Key ◽  
The Internet ◽  
Sensitive Information ◽  
Rsa Algorithm ◽  
Encryption And Decryption ◽  
Main Disadvantage ◽  
Encryption Decryption

To transmit sensitive information over the unsafe communication network like the internet network, the security is precarious tasks to protect this information. Always, we have much doubt that there are more chances to uncover the information that is being sent through network terminals or the internet by professional/amateur parasitical persons. To protect our information we may need a secure way to safeguard our transferred information. So, encryption/decryption, stenographic and vital cryptography may be adapted to care for the required important information. In system cryptography, the information transferred between both sides sender/receiver in the network must be scrambled using the encryption algorithm. The second side (receiver) should be outlook the original data using the decryption algorithms. Some encryption techniques applied the only one key in the cooperation of encryption and decryption algorithms. When the similar key used in both proceeds is called symmetric algorithm. Other techniques may use two different keys in encryption/decryption in transferring information which is known as the asymmetric key.  In general, the algorithms that implicated asymmetric keys are much more secure than others using one key.   RSA algorithm used asymmetric keys; one of them for encryption the message, and is known as a public key and another used to decrypt the encrypted message and is called a private key. The main disadvantage of the RSA algorithm is that extra time is taken to perform the encryption process. In this study, the MATLAB library functions are implemented to achieve the work. The software helps us to hold very big prime numbers to generate the required keys which enhanced the security of transmitted information and we expected to be difficult for a hacker to interfere with the private information. The algorithms are implemented successfully on different sizes of messages files.

scholarly journals Enhanced Algorithm Implementation for Low Powered IoT Devices Using Authenticator to Improve Data Integrity

Webology ◽  
2021 ◽  
Vol 18 (Special Issue 04) ◽  
pp. 733-751
Author(s):  
D.M. Sheeba
Keyword(s):  
Data Security ◽  
Low Cost ◽  
Easy Access ◽  
Raspberry Pi ◽  
Network Availability ◽  
Services Delivery ◽  
Encryption And Decryption ◽  
Arduino Uno ◽  
Iot Devices ◽  
Algorithm Implementation

Internet of Things enables many industries to connect to end customers and provide seamless products and services delivery. Due to easy access to network, availability of devices, penetration of IoT services exponentially Growing. Meanwhile, Ensuring the Data Security and Integrity of devices connected to network is paramount. In this work, we bring the efficient way of implementing Secure Algorithm for low powered devices and enhancing the encryption and decryption process. In addition to the data security, to enhance node integrity with less power, Authenticator and intermediate network manager introduced which will acts as a firewall and manager of data flow. To demonstrate the approach, same is implemented using low cost Arduino Uno, Raspberry Pi boards. Arduino Uno used to demonstrate low powered encryption process using EDIA Algorithm and raspberry pi used as nodal manager to manage the integrity of nodes in a low-powered environment. Data Security and Integrity is ensured by the way of enhanced Algorithm and Integrity through BlockChain and results are provided and discussed. Finally result and future enhancement are explained.

scholarly journals AES WITH CHAOTIC USING CHEBYSHEV POLYNOMIAL

2018 ◽  
Vol 44 (2) ◽  
pp. 35-40
Author(s):  
Tanya jabor ◽  
Hiba Taresh ◽  
Alaa Raheema
Keyword(s):  
Real Time ◽  
Personal Information ◽  
Chaotic Map ◽  
Encryption Algorithm ◽  
The Internet ◽  
Key Generation ◽  
Generation Algorithm ◽  
Critical Data ◽  
Encryption And Decryption ◽  
Day By Day

All the important information is exchanged between facilities using the internet and networks, all these data should besecret and secured probably, the personal information of person in each of these institutions day by day need to organized secretlyand the need of the cryptography systems is raised which can easily encrypt the personal and critical data and it can be shared withother centers via internet without and concerns about privacy. Chaotic performance is added to different phases of AES but very few apply it on key generation and choosing ChebyshevPolynomial will provide a chaotic map which will led to random strong key. our system based on modified advanced encryptionstandard (AES) , with encryption and decryption in real time taking to consideration the criticality of data images that beenencrypted the main encryption algorithm is the same the modification is done by replacing the key generation algorithm byChebyshev Polynomial to generate key with the required key size.

scholarly journals Application of a Lightweight Encryption Algorithm to a Quantized Speech Image for Secure IoT

2018 ◽  
Author(s):  
Mourad Talbi ◽  
Med Salim Bouhalel
Keyword(s):  
Internet Of Things ◽  
Data Security ◽  
Speech Signal ◽  
Block Cipher ◽  
Encryption Algorithm ◽  
Encryption Algorithms ◽  
Computationally Expensive ◽  
Complex Algorithm ◽  
Lightweight Encryption ◽  
Image Simulations

The IoT Internet of Things being a promising technology of the future. It is expected to connect billions of devices. The increased communication number is expected to generate data mountain and the data security can be a threat. The devices in the architecture are fundamentally smaller in size and low powered. In general, classical encryption algorithms are computationally expensive and this due to their complexity and needs numerous rounds for encrypting, basically wasting the constrained energy of the gadgets. Less complex algorithm, though, may compromise the desired integrity. In this paper we apply a lightweight encryption algorithm named as Secure IoT (SIT) to a quantized speech image for Secure IoT. It is a 64-bit block cipher and requires 64-bit key to encrypt the data. This quantized speech image is constructed by first quantizing a speech signal and then splitting the quantized signal into frames. Then each of these frames is transposed for obtaining the different columns of this quantized speech image. Simulations result shows the algorithm provides substantial security in just five encryption rounds.

Hardware Implementation of AES Algorithm with Logic S-box

2017 ◽  
Vol 26 (09) ◽  
pp. 1750141 ◽  
Author(s):  
Soufiane Oukili ◽  
Seddik Bri
Keyword(s):  
Data Security ◽  
High Speed ◽  
Hardware Implementation ◽  
Network Applications ◽  
Aes Algorithm ◽  
Communication Techniques ◽  
High Speed Network ◽  
Cryptographic Algorithm ◽  
Hardware Implementations ◽  
Field Programmable

Cryptography has an important role in data security against known attacks and decreases or limits the risks of hacking information, especially with rapid growth in communication techniques. In the recent years, we have noticed an increasing requirement to implement cryptographic algorithms in fast rising high-speed network applications. In this paper, we present high throughput efficient hardware implementations of Advanced Encryption Standard (AES) cryptographic algorithm. We have adopted pipeline technique in order to increase the speed and the maximum operating frequency. Therefore, registers are inserted in optimal placements. Furthermore, we have proposed 5-stage pipeline S-box design using combinational logic to reach further speed. In addition, efficient key expansion architecture suitable for our proposed design is also presented. In order to secure the hardware implementation against side-channel attacks, masked S-box is introduced. The implementations had been successfully done by virtex-6 (xc6vlx240t) Field-Programmable Gate Array (FPGA) device using Xilinx ISE 14.7. Our proposed unmasked and masked architectures are very fast, they achieve a throughput of 93.73 Gbps and 58.57 Gbps, respectively. The obtained results are competitive in comparison with the implementations reported in the literature.

scholarly journals Parallel impelementation of RC6 algorithm

2021 ◽  
Vol 3 (2) ◽  
pp. 01-09
Author(s):  
Artan Berisha ◽  
Hektor Kastrati
Keyword(s):  
Data Security ◽  
Parallel Implementation ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Block Algorithm ◽  
General Terms ◽  
Encryption And Decryption ◽  
Encryption Algorithms ◽  
Symmetric Block

Data security is very important in the field of Computer Science. In this paper the encryption algorithm called RC6 will be analyzed and its standard and parallel implementation will be done. First the field of Cryptology is discussed in general terms, then the classification of encryption algorithms according to operation and techniques is explained. RC6 is a symmetric block algorithm derived from the RC5 algorithm. RC6 operates on 128-bit blocks and accepts 128, 192, 256-bit keys until 2040 bytes. In the Advanced Encryption Standard (AES) competition, RC6 managed to rank among the five finalists. The structure of the RC6 algorithm will be analyzed also the encryption and decryption methods.  The comparison between standard and parallel implementation will be made.

scholarly journals An Efficient and Highly Secure Technique to Encrypt and Decrypt Color Images

2019 ◽  
Vol 9 (3) ◽  
pp. 4165-4168 ◽  
Author(s):  
M. O. Al-Dwairi ◽  
A. Y. Hendi ◽  
Z. A. AlQadi
Keyword(s):  
Image Encryption ◽  
Color Image ◽  
Color Images ◽  
The Internet ◽  
Security Level ◽  
Color Image Encryption ◽  
Encryption And Decryption ◽  
Encryption Decryption ◽  
Low Efficiency ◽  
Digital Color Images

Digital color images are considered as the most widely used data. They are exchanged frequently on the internet and via email, so an efficient and highly secure method of color image encryption and decryption is needed. Different methods of encryption-decryption are used, but most of them suffer from low efficiency or low-security level or both. In this paper, an efficient and highly secure method of encryption-decryption will be proposed, tested, and implemented. The efficiency parameters will be calculated and compared with other methods’ parameters to prove the efficiency of the proposed method.

scholarly journals New primitives of controlled elements F2/4 for block ciphers

2020 ◽  
Vol 10 (5) ◽  
pp. 5470
Author(s):  
Minh Nguyen Hieu ◽  
Duy Ho Ngoc ◽  
Canh Hoang Ngoc ◽  
Trung Dinh Phuong ◽  
Manh Tran Cong
Keyword(s):  
Building Block ◽  
Hardware Implementation ◽  
Block Cipher ◽  
Block Ciphers ◽  
Differential Analysis ◽  
New Class ◽  
Use Of Data ◽  
Hardware Implementations ◽  
Bit Vector ◽  
Elementary Building

This paper develops the cipher design approach based on the use of data-dependent operations (DDOs). A new class of DDO based on the advanced controlled elements (CEs) is introduced, which is proven well suited to hardware implementations for FPGA devices. To increase the hardware implementation efficiency of block ciphers, while using contemporary FPGA devices there is proposed an approach to synthesis of fast block ciphers, which uses the substitution-permutation network constructed on the basis of the controlled elements F2/4 implementing the 2 x 2 substitutions under control of the four-bit vector. There are proposed criteria for selecting elements F2/4 and results on investigating their main cryptographic properties. It is designed a new fast 128-bit block cipher MM-128 that uses the elements F2/4 as elementary building block. The cipher possesses higher performance and requires less hardware resources for its implementation on the bases of FPGA devices than the known block ciphers. There are presented result on differential analysis of the cipher MM-128

32-bit Datapath AES IP Core Based on FPGA

2013 ◽  
Vol 336-338 ◽  
pp. 1848-1851
Author(s):  
Hong Wei Tang
Keyword(s):  
Finite State Machine ◽  
State Machine ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Ip Core ◽  
Encryption And Decryption ◽  
Finite State ◽  
Encryption Decryption ◽  
Maximum Clock Frequency

This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily.

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