High Level Synthesis Implementation of Real-Time Video Stabilization

2020 ◽  
Author(s):  
Alexander Noce
Keyword(s):  
Real Time ◽  
High Level Synthesis ◽  
Video Stabilization ◽  
High Level

AN EFFICIENT FPGA OVERLAY FOR COLOR TRANSFORMATION FUNCTION USING HIGH LEVEL SYNTHESIS

2021 ◽  
Vol 9 (1) ◽  
pp. 280-287
Author(s):  
Minal Deshmukh, Prasad Khandekar, Nishikant Sadafale
Keyword(s):  
Image Processing ◽  
Real Time ◽  
Transformation Function ◽  
High Level Synthesis ◽  
Smart Devices ◽  
Real Time Image Processing ◽  
Real Time Image ◽  
Color Transformation ◽  
High Level ◽  
Time Image

Image Processing is a significantly desirable in commercial, industrial, and medical applications. Processor based architectures are inappropriate for real time applications as Image processing algorithms are quite intensive in terms of computations. To reduce latency and limitation in performance due to limited amount of memory and fixed clock frequency for synthesis in processor-based architecture, FPGA can be used in smart devices for implementing real time image processing applications. To increase speed of real time image processing custom overlays (Hardware Library of programmable logic circuit) can be designed to run on FPGA fabric. The IP core generated by the HLS (High Level Synthesis) can be implemented on a reconfigurable platform which allows effective utilization of channel bandwidth and storage. In this paper we have presented FPGA overlay design for color transformation function using Xilinx’s python productivity board PYNQ-Z2 to get benefit in performance over a traditional processor. Performance comparison of custom overlay on FPGA and Processor based platform shows FPGA execution yields minimum computation time.

scholarly journals Exploration of FPGA-based electromagnetic transient real-time simulation system design using high-level synthesis

2019 ◽  
Vol 2019 (16) ◽  
pp. 1217-1220 ◽  
Author(s):  
Qiao Li ◽  
Yinxing Xiang ◽  
Qing Mu ◽  
Xing Zhang ◽  
Xiongfei Li ◽  
...  
Keyword(s):  
System Design ◽  
Real Time ◽  
Simulation System ◽  
High Level Synthesis ◽  
Real Time Simulation ◽  
Electromagnetic Transient ◽  
Time Simulation ◽  
High Level

A hardware implementation for real-time lane detection using high-level synthesis

2018 ◽  
Author(s):  
Chanon Khongprasongsiri ◽  
Pinit Kumhom ◽  
Watcharapan Suwansantisuk ◽  
Teerasak Chotikawanid ◽  
Surachate Chumpol ◽  
...  
Keyword(s):  
Real Time ◽  
Hardware Implementation ◽  
Lane Detection ◽  
High Level Synthesis ◽  
High Level

Accelerating Sobel Edge Detection Using Compressor Cells Over FPGAs

2018 ◽  
pp. 1133-1154
Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Video Processing ◽  
High Level Synthesis ◽  
Computational Time ◽  
The Novel ◽  
Image And Video Processing ◽  
Sobel Edge Detection ◽  
High Level ◽  
Time Image

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.

Accelerating Sobel Edge Detection Using Compressor Cells Over FPGAs

2017 ◽  
pp. 1-21
Author(s):  
Ahmed Abouelfarag ◽  
Marwa Ali Elshenawy ◽  
Esraa Alaaeldin Khattab
Keyword(s):  
Edge Detection ◽  
Real Time ◽  
Video Processing ◽  
High Level Synthesis ◽  
Computational Time ◽  
The Novel ◽  
Image And Video Processing ◽  
Sobel Edge Detection ◽  
High Level ◽  
Time Image

Recently, computer vision is playing an important role in many essential human-computer interactive applications, these applications are subject to a “real-time” constraint, and therefore it requires a fast and reliable computational system. Edge Detection is the most used approach for segmenting images based on changes in intensity. There are various kernels used to perform edge detection, such as: Sobel, Robert, and Prewitt, upon which, the most commonly used is Sobel. In this research a novel type of operator cells that perform addition is introduced to achieve computational acceleration. The novel operator cells have been employed in the chosen FPGA Zedboard which is well-suited for real-time image and video processing. Accelerating the Sobel edge detection technique is exploited using different tools such as the High-Level Synthesis tools provided by Vivado. This enhancement shows a significant improvement as it decreases the computational time by 26% compared to the conventional adder cells.

A Hardware–Software Co-Design Framework for Real-Time Video Stabilization

2019 ◽  
Vol 29 (02) ◽  
pp. 2050027
Author(s):  
Hassan Javed ◽  
Muhammad Bilal ◽  
Shahid Masud
Keyword(s):  
Real Time ◽  
Video Stream ◽  
Video Stabilization ◽  
Design Framework ◽  
Local Motion ◽  
Video Frames ◽  
Key Points ◽  
Implementation Scheme ◽  
Computationally Intensive ◽  
High Level

Live digital video is a valuable source of information in security, broadcast and industrial quality control applications. Motion jitter due to camera and platform instability is a common artefact found in captured video which renders it less effective for subsequent computer vision tasks such as detection and tracking of objects, background modeling, mosaicking, etc. The process of algorithmically compensating for the motion jitter is hence a mandatory pre-processing step in many applications. This process, called video stabilization, requires estimation of global motion from consecutive video frames and is constrainted by additional challenges such as preservation of intentional motion and native frame resolution. The problem is exacerbated in the presence of local motion of foreground objects and requires robust compensation of the same. As such achieving real-time performance for this computationally intensive operation is a difficult task for embedded processors with limited computational and memory resources. In this work, development of an optimized hardware–software co-design framework for video stabilization has been investigated. Efficient video stabilization depends on the identification of key points in the frame which in turn requires dense feature calculation at the pixel level. This task has been identified to be most suitable for offloading the pipelined hardware implemented in the FPGA fabric due to the involvement of complex memory and computation operations. Subsequent tasks to be performed for the overall stabilization algorithm utilize these sparse key points and have been found to be efficiently handled in the software. The proposed Hardware–Software (HW–SW) co-design framework has been implemented on Zedboard FPGA platform which houses Xilinx Zynq SOC equipped with ARM A9 processor. The proposed implementation scheme can process real-time video stream input at 28 frames per second and is at least twice faster than the corresponding software-only approach. Two different hardware accelerator designs have been implemented using different high-level synthesis tools using rapid prototyping principle and consume less than 50% of logic resources available on the host FPGA while being at least 30% faster than contemporary designs.

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