scholarly journals An Ising Hamiltonian Solver using Stochastic Phase-Transition Nano-Oscillators

2020 ◽  
Author(s):  
Sourav Dutta ◽  
Abhishek Khanna ◽  
Hanjong Paik ◽  
Darrell Schlom ◽  
Arijit Raychowdhury ◽  
...  

Abstract Computationally hard problems, including combinatorial optimization, can be mapped into the problem of finding the ground-state of an Ising Hamiltonian. Building physical systems with collective computational ability and distributed parallel processing capability can accelerate the ground-state search. Here, we present a continuous-time dynamical system (CTDS) approach where the ground-state solution appears as stable points or attractor states of the CTDS. We harness the emergent dynamics of a network of phase-transition nano-oscillators (PTNO) to build an Ising Hamiltonian solver. The hardware fabric comprises of electrically coupled injection-locked stochastic PTNOs with bi-stable phases emulating artificial Ising spins. We demonstrate the ability of the stochastic PTNO-CTDS to progressively find more optimal solution by increasing the strength of the injection-locking signal – akin to performing classical annealing. We demonstrate in silico that the PTNO-CTDS prototype solves a benchmark non-deterministic polynomial time (NP)-hard Max-Cut problem with high probability of success. Using experimentally calibrated numerical simulations, we investigate the performance of the hardware with increasing problem size. We show the best-in-class energy-efficiency of 3.26x107 solutions/sec/Watt which translates to over five orders of magnitude improvement when compared with digital CMOS, superconducting qubit and photonic Ising solver approaches. We also demonstrate an order of magnitude improvement over a discrete-time memristor-based Hopfield network approach. Such an energy efficient CTDS hardware exhibiting high solution-throughput/Watt can find application in industrial planning and manufacturing, defense and cyber-security, bioinformatics and drug discovery.

2020 ◽  
Author(s):  
Xiaoyuan Wang ◽  
Pengfei Zhou ◽  
Jason Eshraghian ◽  
Chih-Yang Lin ◽  
Herbert Ho-Ching Iu ◽  
...  

<div>This paper presents the first experimental demonstration</div><div>of a ternary memristor-CMOS logic family. We systematically</div><div>design, simulate and experimentally verify the primitive</div><div>logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance.</div>


2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Quanjun Yin ◽  
Long Qin ◽  
Xiaocheng Liu ◽  
Yabing Zha

In robotics, Generalized Voronoi Diagrams (GVDs) are widely used by mobile robots to represent the spatial topologies of their surrounding area. In this paper we consider the problem of constructing GVDs on discrete environments. Several algorithms that solve this problem exist in the literature, notably the Brushfire algorithm and its improved versions which possess local repair mechanism. However, when the area to be processed is very large or is of high resolution, the size of the metric matrices used by these algorithms to compute GVDs can be prohibitive. To address this issue, we propose an improvement on the current algorithms, using pointerless quadtrees in place of metric matrices to compute and maintain GVDs. Beyond the construction and reconstruction of a GVD, our algorithm further provides a method to approximate roadmaps in multiple granularities from the quadtree based GVD. Simulation tests in representative scenarios demonstrate that, compared with the current algorithms, our algorithm generally makes an order of magnitude improvement regarding memory cost when the area is larger than210×210. We also demonstrate the usefulness of the approximated roadmaps for coarse-to-fine pathfinding tasks.


2017 ◽  
Vol 56 (24) ◽  
pp. 14842-14849 ◽  
Author(s):  
Liurukara D. Sanjeewa ◽  
Vasile O. Garlea ◽  
Michael A. McGuire ◽  
Matthias Frontzek ◽  
Colin D. McMillen ◽  
...  

1992 ◽  
Vol 17 (1) ◽  
pp. 107-110
Author(s):  
Shun-Qing Shen ◽  
J. Cai ◽  
Rui-Bao Tao

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