Incremental Methods for Formal Verification and Logic Synthesis

1996 ◽  
Author(s):  
Gitanjali Swamy
Keyword(s):  
Formal Verification ◽  
Logic Synthesis ◽  
Incremental Methods

Formal Verification of Control System Software

2019 ◽  
Author(s):  
Pierre-Loïc Garoche
Keyword(s):  
Control System ◽  
Formal Verification ◽  
Formal Analysis ◽  
Critical Systems ◽  
System Software ◽  
Unified Approach ◽  
Verification Methods ◽  
Autonomous Cars ◽  
Computer Scientists ◽  
Verification Techniques

The verification of control system software is critical to a host of technologies and industries, from aeronautics and medical technology to the cars we drive. The failure of controller software can cost people their lives. This book provides control engineers and computer scientists with an introduction to the formal techniques for analyzing and verifying this important class of software. Too often, control engineers are unaware of the issues surrounding the verification of software, while computer scientists tend to be unfamiliar with the specificities of controller software. The book provides a unified approach that is geared to graduate students in both fields, covering formal verification methods as well as the design and verification of controllers. It presents a wealth of new verification techniques for performing exhaustive analysis of controller software. These include new means to compute nonlinear invariants, the use of convex optimization tools, and methods for dealing with numerical imprecisions such as floating point computations occurring in the analyzed software. As the autonomy of critical systems continues to increase—as evidenced by autonomous cars, drones, and satellites and landers—the numerical functions in these systems are growing ever more advanced. The techniques presented here are essential to support the formal analysis of the controller software being used in these new and emerging technologies.

Algorithm of Optimizing Quantum Reversible Logic Synthesis

2009 ◽  
Vol 20 (9) ◽  
pp. 2332-2343
Author(s):  
Zhi-Qiang LI ◽  
Wen-Qian LI ◽  
Han-Wu CHEN
Keyword(s):  
Logic Synthesis ◽  
Reversible Logic ◽  
Reversible Logic Synthesis

HOL2GDT a Formal Verification-Based Design Methodology

2001 ◽  
Author(s):  
Anand Chavan ◽  
Byoung Woo Min ◽  
Shiu-Kai Chin
Keyword(s):  
Formal Verification ◽  
Design Methodology

Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation

2019 ◽  
Vol 12 (1) ◽  
pp. 30-39 ◽  
Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan
Keyword(s):  
Integrated Circuits ◽  
Power Density ◽  
Logic Synthesis ◽  
Programmable Logic Arrays ◽  
Power Switching ◽  
Nsga Ii ◽  
Multi Level ◽  
Search Approach ◽  
Efficient Power ◽  
The Impact

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.

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