scholarly journals Design of a Regular Expression Matching System Based on Network on Chip

2013 ◽  
Vol 7 (1) ◽  
pp. 46-50
Author(s):  
Linhai Cui ◽  
Yusen Qin ◽  
Fanyang Kong ◽  
Kaihong Yu
Keyword(s):  
Integrated Circuits ◽  
Regular Expression ◽  
General Purpose ◽  
Network On Chip ◽  
Deep Packet Inspection ◽  
Regular Expression Matching ◽  
Finite State ◽  
Ip Cores ◽  
Packet Inspection ◽  
On Chip

This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

scholarly journals Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

2019 ◽  
Vol 63 (4) ◽  
pp. 244-253
Author(s):  
Jagadeesh Kokila ◽  
Arjun Murali Das ◽  
Basha Shameedha Begum ◽  
Natarajan Ramasubramanian
Keyword(s):  
Intellectual Property ◽  
Integrated Circuits ◽  
Full Adder ◽  
Hardware Trojan ◽  
Signature Generation ◽  
Finite State ◽  
Arbiter Puf ◽  
Ip Cores ◽  
On Chip ◽  
Random Responses

Security is becoming an important issue in the recent System on Chip (SoC) design due to various hardware attacks that can affect manufacturers, system designers or end users. Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks. A hybrid model consisting of Arbiter PUF and Butterfly PUF are used to generate random responses which are fed to a Finite State Machine (FSM). A three-level FSM was designed to generate the signature correctly to authenticate IPs. The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS’89 s1423 Benchmark IP and a Full Adder IP. A 16-bit arbiter PUF and Butterfly PUF have been implemented on a 28nm FPGA. The average execution time to generate hardware signature for three IP cores was found to be 4.78 seconds (5 iterations) which is considerably low.

scholarly journals Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design

Sensors ◽  
2019 ◽  
Vol 19 (24) ◽  
pp. 5416 ◽  
Author(s):  
Douglas R. Melo ◽  
Cesar A. Zeferino ◽  
Luigi Dilillo ◽  
Eduardo A. Bezerra
Keyword(s):  
Integrated Circuits ◽  
Error Propagation ◽  
Fault Tolerant ◽  
Propagation Rate ◽  
Network On Chip ◽  
Space Applications ◽  
Component Size ◽  
Finite State ◽  
On Chip ◽  
Modular Redundancy

Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.

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