Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design

Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.

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Design of a Regular Expression Matching System Based on Network on Chip

The Open Electrical & Electronic Engineering Journal ◽

10.2174/1874129001307010046 ◽

2013 ◽

Vol 7 (1) ◽

pp. 46-50

Author(s):

Linhai Cui ◽

Yusen Qin ◽

Fanyang Kong ◽

Kaihong Yu

Keyword(s):

Integrated Circuits ◽

Regular Expression ◽

General Purpose ◽

Network On Chip ◽

Deep Packet Inspection ◽

Regular Expression Matching ◽

Finite State ◽

Ip Cores ◽

Packet Inspection ◽

On Chip

This paper presents an efficient method for Regular Expression Matching (REM) by reusing Intellectual Property (IP) cores in a new architecture of Network on Chip (NoC). The method is to design a reusable IP core which consists of many engine cells for REM and to implement each engine cell on a Field Programmable Gate Array (FPGA) as a prototype. To make Finite State Machine (FSM) simpler, a new approach for partitioning a regular expression into several smaller parts is proposed. Each part of a regular expression was matched by an engine cell during matching, and each engine cell communicates with others by routers on a NoC topology. The proposed NoC architecture is a general-purpose design which is suitable for different rule libraries in deep packet inspection (DPI). It can deal with the problem that character self-deplete made the correct regular expression matching missing. A way to use both logic cell and RAM available on FPGA devices is described, and it can make it easier to change the rule library of regular expressions in the RAM. The implementation of the NoC architecture by employing application-specific integrated circuits (ASIC) is finally discussed.

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SpaceWire Inspired Network-on-Chip Approach for Fault Tolerant System-on-Chip Designs

Dynamic Reconfigurable Network-on-Chip Design ◽

10.4018/978-1-61520-807-4.ch012 ◽

2010 ◽

pp. 293-308

Author(s):

Björn Osterloh ◽

Harald Michalik ◽

Björn Fiethe

Keyword(s):

Fault Tolerant ◽

High Reliability ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

System On Chip ◽

Space Applications ◽

Communication Architecture ◽

Radiation Induced ◽

And Performance ◽

On Chip

Today FPGAs with large gate counts provide a highly flexible platform to implement a complete System-on-Chip (SoC) in a single device. Specifically radiation tolerant space suitable SRAM-based FPGAs have significantly improved the flexibility of high reliable systems for space applications. Currently the reconfigurability of these devices is only used during development phase. A further enhancement would be using the reconfigurability of SRAM-FPGAs in space, either to statically update or dynamically reconfigure processing modules. This is a major improvement in terms of maintenance and performance, which is essential for scientific instruments in space. The requirement for this enhanced system is to guarantee the system qualification and retain the achieved high reliability. Therefore effects during the reconfiguration process and interference of updated modules on the system have to be prevented. Updated modules need to be isolated physically and logically by qualified communication architecture. In this chapter the advantage of a specialized Network-on-Chip architecture to achieve a high reliable SoC with dynamic reconfiguration capability is presented. The requirements for SoC based on SRAM-FPGA in high reliable applications are outlined. Additionally the influences of radiation induced particles are described and effects during the dynamic reconfiguration are discussed. A specialized Network-on-Chip architecture is then proposed and its advantages are presented.

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