Parasitic Inductance Design Considerations to Suppress Gate Voltage Oscillation of Fast Switching Power Semiconductor Devices
2013 ◽
Vol 28
(11)
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pp. 5423-5430
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Keyword(s):
Keyword(s):
Keyword(s):
2010 ◽
Vol 130
(6)
◽
pp. 911-911
2014 ◽
Vol 134
(6)
◽
pp. 432-433
2019 ◽
Vol 139
(2)
◽
pp. 76-79