Thermal and Electrical Co-Optimization of a Multi-Chip Double-Sided Cooled GaN Module

The need for high power density electrical converters/inverters dominates the power electronics realm, and wide bandgap semiconducting materials, such as gallium nitride (GaN), provide the enhanced material properties necessary to drive at higher switching speeds than traditional silicon. However, lateral GaN devices introduce packaging difficulties, especially when attempting a double-sided cooled solution. Herein, we describe optimization efforts for a 650V/30A, GaN half-bridge power module with an integrated gate driver and double-sided cooling capability. Two direct bonded copper (DBC) substrates provided the primary means of heat removal from the module. In addition to the novel topology, the team performed electrical/thermal co-design to increase the multi-functionality of module. Since a central PCB comprised the main power loop, the size and geometry of the vias and copper traces was analyzed to determine optimal functionality in terms of parasitic inductance and thermal spreading. Thermally, thicker copper layers and additional vias introduced into the PCB also helped reduce hot spots within the module. Upon fabrication of the module, it underwent electrical characterization to determine switching performance, as well as thermal characterization to experimentally measure the total module’s thermal resistance. The team successfully operated the module at 400 V, 30 A with a power loop parasitic inductance of 0.89 nH; experimental thermal measurements also indicated the module thermal resistance to be 0.43 C/W. The overall utility of the design improved commensurately by introducing simple, yet effective electrical/thermal co-design strategies, which can be applied to future power modules.

Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Lumped Parameter Modeling Based Power Loop Analysis Technique of Power Circuit Board with Wide Conduction Area for WBG Semiconductors

With the development of wide-bandgap (WBG) power semiconductor technology, such as silicon carbide (SiC) and gallium nitride (GaN), the technology of power converters with high efficiency and high-power density is rapidly developing. However, due to the high rate-of-rise of voltage (dv/dt) and of current (di/dt), compared to conventional Si-based power semiconductor devices, the reliability of the device is greatly affected by the parasitic inductance component in the switching loop. In this paper, we propose a power loop analysis method based on lumped parameter modeling of a power circuit board with a wide conduction area for WBG power semiconductors. The proposed analysis technique is modeled based on lumped parameters, so that power loops with various current paths can be analyzed; thus, the analysis is intuitive, easy to apply and realizes dynamic power loop analysis. Through the proposed analysis technique, it is possible to derive the effective parasitic inductance component for the main points in the power circuit board. The effectiveness of the lumped parameter model is verified through PSpice and Ansys Q3D simulation results.