In this paper, novel low and high frequency performance improvement techniques are proposed. High frequency performance improvement method is based on the single pole effect reduction/completely elimination by creating a corresponding zero while a low one is based on reduction/elimination of Z terminal parasitic resistors. Therefore, two grounded capacitance multipliers, three grounded inductor simulators, a floating inductor and a voltage-mode (VM) universal filter using second-generation current conveyors (CCIIs) are used to explain the developed methods. One of the grounded inductor simulators, floating simulated inductor and VM biquad are novel. Further, both of the new simulated inductors use a grounded capacitor; accordingly, they are suitable for IC fabrication. However, all the proposed circuits need a single matching condition. A number of simulations through PSPICE program and experimental tests are accomplished to demonstrate the workability, performance and effectiveness.
Enhanced High-Frequency Performance of Top-Gated Graphene FETs Due to Substrate-Induced Improvements in Charge Carrier Saturation Velocity
