scholarly journals Cost Analysis and Simulation of Decimator for Multirate Applications

2013 ◽  
Vol 11 (1) ◽  
pp. 2175-2181
Author(s):  
Rajesh Mehra ◽  
Lajwanti Singh
Keyword(s):  
Signal Processing ◽  
Cost Analysis ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Cost Effective ◽  
Resource Consumption ◽  
Cost Comparison ◽  
Effective Solution ◽  
Symmetric Structure ◽  
Direct Form

In this paper, a decimator design has been presented for multirate digital signal processing.  The decimator design has been analysed and simulated for cost comparison in terms of multipliers and MPIS. Two structures  namely Transposed Direct form and Symmetric Direct form have been used performance and  resource consumption analysis. The decimators have been designed  & simulated using MATLAB. It can be observed from the simulated results that symmetric structure comsumes almost 50% less multipliers and MPIS compared to transposed structure. So the symmetric structure based decimator is suitable to provide cost effective solution

scholarly journals Border Handling for 2D Transpose Filter Structures on an FPGA

2018 ◽  
Vol 4 (12) ◽  
pp. 138 ◽  
Author(s):  
Donald Bailey ◽  
Anoop Ambikumar
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Linear Filters ◽  
Filter Structure ◽  
Direct Form ◽  
Two Stages ◽  
Filter Structures ◽  
Zero Extension

It is sometimes desirable to implement filters using a transpose-form filter structure. However, managing image borders is generally considered more complex than it is with the more commonly used direct-form structure. This paper explores border handling for transpose-form filters, and proposes two novel mechanisms: transformation coalescing, and combination chain modification. For linear filters, coefficient coalescing can effectively exploit the digital signal processing blocks, resulting in the smallest resources requirements. Combination chain modification requires similar resources to direct-form border handling. It is demonstrated that the combination chain multiplexing can be split into two stages, consisting of a combination network followed by the transpose-form combination chain. The resulting transpose-form border handling networks are of similar complexity to the direct-form networks, enabling the transpose-form filter structure to be used where required. The transpose form is also significantly faster, being automatically pipelined by the filter structure. Of the border extension methods, zero-extension requires the least resources.

Research and Application of a FPGA-Based Dynamic Distributed Algorithm

2011 ◽  
Vol 58-60 ◽  
pp. 1696-1700
Author(s):  
Wei Zheng Ren ◽  
Ying Gao ◽  
Yan Song Cui
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Processing Speed ◽  
Distributed Algorithm ◽  
Digital Signal ◽  
Fir Filter ◽  
Effective Solution ◽  
Data Bus

A dynamic distributed algorithm (DDA) with a look-up dynamic table instead of ROM was put forward based on the theory of signed distributed algorithm, in order to improve processing speed and flexibility of product sum on FPGA. Since the DDA occupies few hardware resources, performs fast operation and realizes programmable coefficient, the limitation of digital signal processing speed on fixed data bus width and sequential operation was avoided by using the algorithm. At the same time, an effective solution to realizing coefficient programmable FIR filter was presented.

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