scholarly journals DESIGN AND IMPLEMENTATION OF FPGA-BASED FFT CO-PROCESSOR USING VERILOG HARDWARE DESCRIPTION LANGUAGE

2021 ◽  
Vol 92 ◽  
pp. 47-70
Author(s):  
Yung-Chong Lee ◽  
Yee Kit Chan ◽  
Voon Chet Koo
Keyword(s):  
Hardware Description Language ◽  
Description Language ◽  
Design And Implementation ◽  
Hardware Description ◽  
Verilog Hardware Description Language

Improved Redundant Binary Adder Realization in FPGA

2021 ◽  
pp. 2150287
Author(s):  
Satya Ranjan Sahu ◽  
Bandan Kumar Bhoi ◽  
Manoranjan Pradhan
Keyword(s):  
Propagation Delay ◽  
Hardware Description Language ◽  
Binary Number ◽  
Performance Parameters ◽  
Description Language ◽  
Hardware Description ◽  
Verilog Hardware Description Language

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.

scholarly journals Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA

2019 ◽  
Vol 8 (9S2) ◽  
pp. 512-514
Keyword(s):  
Power Consumption ◽  
Leakage Power ◽  
The Other ◽  
Hardware Description Language ◽  
Description Language ◽  
Power Variation ◽  
Address Register ◽  
Hardware Description ◽  
Verilog Hardware Description Language

In this paper, we are designing an address register which is sensitive towards rising in voltage. We analysed the power variation of address register on Xilinx 14.1 ISE Design Suite and the code of address register is written in Verilog hardware description language. In this paper, we have used two FPGA of two different families, one is of Virtex family which is Virtex 6 and the other is of Spartan family which is Spartan 6, to study the power consumption of address register. We have observed the different on chips power which are consumed by address register by varying the voltage from 0.75V to 2V for Virtex 6 FPGA and 0.75V to 3V for Spartan 6 FPGA and we observed that when we lower the voltage, lower will be the power consumption. At 2V, Virtex 6 FPGA stops working and the interface of address register with FPGA burns out. For Spartan 6 FPGA, the same happens at 3V voltage.

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