Improved Redundant Binary Adder Realization in FPGA

This paper presents the design of improved redundant binary adder (IRBA) by utilizing positive–negative encoding rules in FPGA platform. The proposed design deals with inverted encoding of negative binary (IEN) and positive binary number to get addition result using readily available standard hardware module. The Verilog hardware description language is used as design entry for synthesis of the proposed architecture in Xilinx ISE Desisn Suite 14.4 software. This structure is realized on Vertex-4 xc4vfx12-12sf363 FPGA device. The proposed IRBA is found to be time efficient in comparison with the performance parameters such as propagation delay and area over previous reported architecture.

Random-access memory coding in the Verilog description language for solving problems in radio electronics and mechanical engineering

The article proposes a variant of writing an algorithm for the operation of a device used in a field-programmable gate array on the example of random-access memory coding using the Verilog hardware description language. When performing the work, the Xilinx software is used, which allows working with the project at all stages of creating and describing the operation of the device logic. The practical significance of the work is the study and solution of the simplest problems in the development of modern radioelectronic rapid response devices in the Verilog hardware description language, such as coding a field-programmable gate array itself, writing test debugging code, setting input and output signals, sync pulse, reset and enable signals, describing the logic of devices such as counters, switches, registers and triggers, as well as simulating a finished project to assess the correct operation of the programmed device. This work can be used not only for teaching students of higher educational institutions in the field of development, debugging and coding of electronic and radio-electronic devices in terms of describing the algorithm of their work, but also for organizing laboratory work on courses of disciplines related to this topic, and for creating and designing real devices in production. The introduction and study of this programming language are conducted within the walls of one of the leading engineering universities of the Russian Federation — the Bauman Moscow State Technical University.

Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA

In this paper, we are designing an address register which is sensitive towards rising in voltage. We analysed the power variation of address register on Xilinx 14.1 ISE Design Suite and the code of address register is written in Verilog hardware description language. In this paper, we have used two FPGA of two different families, one is of Virtex family which is Virtex 6 and the other is of Spartan family which is Spartan 6, to study the power consumption of address register. We have observed the different on chips power which are consumed by address register by varying the voltage from 0.75V to 2V for Virtex 6 FPGA and 0.75V to 3V for Spartan 6 FPGA and we observed that when we lower the voltage, lower will be the power consumption. At 2V, Virtex 6 FPGA stops working and the interface of address register with FPGA burns out. For Spartan 6 FPGA, the same happens at 3V voltage.