ABOUT CONSTRUCTION OF A UNIFIED INFORMATION ADDRESS SYSTEM OF UKRAINE

The problem of Address registers of settlements according to uniform rules and single a unified State information address system is acute on the agenda in the last decade. Addresses are a component of many cadasters and registers that have been created and operate in Ukraine today. The problem of creating the Unified Address system of Ukraine is exacerbated in the conditions of accelerated digital transformation of public relations. The analysis of recent research and publications allowed to characterize the state of creation of the Unified Address Register of Ukraine as unsatisfactory, revealed shortcomings and lack of a common vision of aspects of addressing issues. A new comprehensive solution to the problems of targeted issues is proposed - the construction of a single unified State information address system. Substantiated and presented common approaches, understandings, definitions, structure and relations of address data are the conceptual provisions of the construction of a single unified State information address system and the basis for the development, approval, adoption at the legislative level. The construction of a conceptual model of address data is based primarily on the internationally established specifications of address data used in Infrastructure for Spatial Information in the European Community (INSPIRE) and the National Geospatial Data Infrastructure of Ukraine. The address system is defined as an information system, that consists of a set of interacting four structural components: 1) addresses, 2) a single address register, 3) address points, 4) address electronic services. The address system performs the functions of identifying the object of addressing, identifying the location of objects of addressing, ensuring the interaction of registers, creating an information address resource of the state, mapping the object of addressing, providing search for the location of the object of addressing. The concept proposes to use the Geographical Identifier of real estate objects of the established structure and addresses, which creates conditions for joint processing of real estate data in geographic information systems and the introduction of a single address register.

Genotype−Environment Correlation and Its Relation to Personality — A Twin and Family Study

The aim of the study was to examine the Family and School Psychosocial Environment (FSPE) questionnaire in relation to a possible genotype–environment correlation and genetic mediation between the FSPE variables and personality variables, assessed by the Junior Eysenck Personality Questionnaire. A sample of 506 Swedish children aged 10–20 years from 253 families were recruited via the Swedish state population and address register and SchoolList.Eu. The children were divided into 253 pairs: 46 monozygotic twin pairs, 42 dizygotic twin pairs, 140 pairs of full siblings and 25 pairs of half-siblings. The behavioral genetic analysis showed that both FSPE factors, Warmth and Conflicts, may be partly influenced by genetic factors (suggesting genotype–environment correlation) and that nonadditive genetic factors may mediate the relationship between FSPE factors and psychoticism/antisocial personality (P). An indication of a special shared monozygotic twin environment was found for P and Lie/social desirability, but based on prior research findings this factor may have a minor influence on P and L. P and L were negatively correlated, and the relationship seems to be partly mediated by nonadditive genetic factors. Nonshared environment and measurement errors seem to be the most influential mediating factors, but none of the cross-twin cross-dimension correlations suggest a common shared environmental mediating factor.

Leakage Power Consumption of Address Register Interfacing with Different Families of FPGA

In this paper, we are designing an address register which is sensitive towards rising in voltage. We analysed the power variation of address register on Xilinx 14.1 ISE Design Suite and the code of address register is written in Verilog hardware description language. In this paper, we have used two FPGA of two different families, one is of Virtex family which is Virtex 6 and the other is of Spartan family which is Spartan 6, to study the power consumption of address register. We have observed the different on chips power which are consumed by address register by varying the voltage from 0.75V to 2V for Virtex 6 FPGA and 0.75V to 3V for Spartan 6 FPGA and we observed that when we lower the voltage, lower will be the power consumption. At 2V, Virtex 6 FPGA stops working and the interface of address register with FPGA burns out. For Spartan 6 FPGA, the same happens at 3V voltage.

USE OF THE ADDRESS REGISTER DATA IN LOCATIONBASED SERVICES

Address register is one of the basic and most commonly used spatial data records. One of its uses is finding addresses in location-based services (geocoding), which for the specified address (city, street, number) return the position in the form of coordinates. The paper presents a comparison of two services: ULA (Usługa Lokalizacji Adresów from Geo-System) and OpenLS (available as a part of the Polish national geoportal). The analysis includes both theoretical aspects (amount of data in the resource, its timeliness, documentation, request and response formats), as well as practical - in the form of testing the performance and accuracy of both services.

Realization of Email Address Register Validation on Engineering Machinery Service Platform

This paper describes the Realization of ASP.net technology on Engineering Machinery Service (EMS) platform, based on environment of Visual Studio 2005. The EMS platform is designed to keep the accuracy of users’ information when registering as well as to filter malicious users who register with fictitious information. During the register process, EMS platform realizes the validation function of Email address which can provide better protection for the website and also inform users of precise information.

CODE SIZE REDUCTION FOR ARRAY INTENSIVE APPLICATIONS ON DIGITAL SIGNAL PROCESSORS

Optimizing the code size for applications that run on a digital signal processors (DSPs) is a crucial step in generating high-quality and efficient code. Most modern DSP provide multiple address registers and dedicated address generation units that provide address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range of the address register. Many DSP algorithms have an iterative pattern of references to array elements within loops. Thus, a careful assignment of array references to address registers (called the address register allocation or ARA problem) reduces the number of explicit address arithmetic instructions as well as the execution cycles. In this paper, we present an optimal integer linear programming formulation for the address register allocation problem which incorporates code restructuring techniques. In addition, we have developed a Genetic Algorithm solution for the ARA problem that allows us to get near-optimal solutions in a reasonable amount of time for large embedded applications. Results on several benchmarks show the effectiveness of our techniques compared to other techniques in the literature.