scholarly journals DESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION

2017 ◽  
Vol 24 (4) ◽  
pp. 393-406
Author(s):  
Md. Shabiul Islam ◽  
M.S. Bhuyan ◽  
M. Salim Beg ◽  
Masuri Othman
Keyword(s):  
Signal Processing ◽  
Image Compression ◽  
Digital Signal ◽  
Design Flow ◽  
System Specification ◽  
Design Environment ◽  
Levels Of Abstraction ◽  
Chip Area ◽  
Design And Implementation ◽  
The Cost

This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT) to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.). The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip

scholarly journals Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits

Computers ◽  
2022 ◽  
Vol 11 (1) ◽  
pp. 11
Author(s):  
Padmanabhan Balasubramanian ◽  
Raunaq Nayar ◽  
Okkar Min ◽  
Douglas L. Maskell
Keyword(s):  
Software Tool ◽  
Digital Signal ◽  
Automatic Generation ◽  
Arithmetic Circuits ◽  
Design Flow ◽  
Attractive Alternative ◽  
Design Environment ◽  
Verilog Hdl ◽  
Arithmetic Circuit ◽  
Practical Applications

Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.

scholarly journals IMPLEMENTATION OF CORRELATION ANALYSIS TASK IN THE MULTICHANNEL STRUCTURE

2006 ◽  
Vol 35 (3) ◽  
Author(s):  
Arūnas Žvironas ◽  
Egidijus Kazanavičius
Keyword(s):  
Signal Processing ◽  
Heterogeneous Systems ◽  
Large Data ◽  
Digital Signal ◽  
Optimal Number ◽  
Heterogeneous Architecture ◽  
Analysis Task ◽  
Data Flows ◽  
The Cost ◽  
Channel Structures

The digital signal processing in general case may be implemented on multi-channel structures. In most cases such structures have a heterogeneous architecture where the Kahn network and correlation are used to process the data flows. In this paper the methodology of the design of heterogeneous systems is presented. The methodology was tested on the design of the real devices controlling large data flows. Multi-channel structures were used to estimate the influence of the number of channels on the speed of data and the cost of the task, and to estimate an optimal number of channels.

scholarly journals Review of Rounding Based Approximate Multiplier (ROBA) For Digital Signal Processing

2019 ◽  
Vol 7 (4) ◽  
pp. 04-07
Author(s):  
Monika Malviya ◽  
Prof. Pankaj Vyas
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
Fundamental Idea ◽  
The Cost

The fundamental idea of adjusting put together estimated multiplier depends with respect to adjusting of numbers. This multiplier can be connected for both marked and unsigned numbers. In this paper contemplated an Rounding Based Approximate Multiplier that is fast yet vitality effective. The methodology is to round the operands to the closest example of two. Along these lines the computational concentrated piece of the augmentation is excluded improving rate and vitality utilization at the cost of a little mistake. This methodology is appropriate to both marked and unsigned augmentations. The productivity of the ROBA multiplier is assessed by contrasting its execution and those of some rough and precise multipliers utilizing distinctive plan parameters.

scholarly journals Design of on-chip temperature-based digital signal processing for customized wireless microcontroller

2019 ◽  
Vol 14 (2) ◽  
pp. 653
Author(s):  
S.F. R. Faezal ◽  
M. N. Isa ◽  
S. Taking ◽  
S. N. Mohyar ◽  
A. B. Jambek ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal ◽  
System On Chip ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Chip Design ◽  
Chip Area ◽  
Monitoring Process ◽  
On Chip

<span>Dramatic rises in power density and die sizes inside system-on-chip (SoC) design have led to the thermal issue. High temperatures or uneven temperature distributions may result not only in reliability issues, also has become the biggest issue that can limit the system performance.  This paper presents the design and simulation of a temperature-based digital signal processing unit for modern system-on-chip design using the Verilog HDL. This design provides continuous monitoring of temperature and reacts to specified conditions. The simulation of the system has been done on Synopsys Software. The result showed that temperature monitoring process is within the temperature range due to the incorporation of an interrupt-based system and with an advantage of minimum chip area required.</span>

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