scholarly journals Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits

Computers ◽  
2022 ◽  
Vol 11 (1) ◽  
pp. 11
Author(s):  
Padmanabhan Balasubramanian ◽  
Raunaq Nayar ◽  
Okkar Min ◽  
Douglas L. Maskell
Keyword(s):  
Software Tool ◽  
Digital Signal ◽  
Automatic Generation ◽  
Arithmetic Circuits ◽  
Design Flow ◽  
Attractive Alternative ◽  
Design Environment ◽  
Verilog Hdl ◽  
Arithmetic Circuit ◽  
Practical Applications

Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.

scholarly journals DESIGN AND IMPLEMENTATION OF A VHDL PROCESSOR FOR DCT BASED IMAGE COMPRESSION

2017 ◽  
Vol 24 (4) ◽  
pp. 393-406
Author(s):  
Md. Shabiul Islam ◽  
M.S. Bhuyan ◽  
M. Salim Beg ◽  
Masuri Othman
Keyword(s):  
Signal Processing ◽  
Image Compression ◽  
Digital Signal ◽  
Design Flow ◽  
System Specification ◽  
Design Environment ◽  
Levels Of Abstraction ◽  
Chip Area ◽  
Design And Implementation ◽  
The Cost

This paper describes the design and implementation of a VHDL processor meant for performing 2D-Discrete Cosine Transform (DCT) to use in image compression applications. The design flow starts from the system specification to implementation on silicon and the entire process is carried out using an advanced workstation based design environment for digital signal processing. The software allows the bit-true analysis to ensure that the designed VLSI processor satisfies the required specifications. The bit-true analysis is performed on all levels of abstraction (behavior, VHDL etc.). The motivation behind the work is smaller size chip area, faster processing, reducing the cost of the chip

scholarly journals Design of Power Efficient 32-Bit Processing Unit

2018 ◽  
Vol 7 (2.16) ◽  
pp. 52
Author(s):  
Dharmavaram Asha Devi ◽  
Chintala Sandeep ◽  
Sai Sugun L
Keyword(s):  
Low Power ◽  
System Design ◽  
Power Analysis ◽  
Low Power Design ◽  
Design Flow ◽  
Processing Unit ◽  
Verilog Hdl ◽  
Power Efficient ◽  
Front End ◽  
Verification Process

The proposed paper is discussed about the design, verification and analysis of a 32-bit Processing Unit.  The complete front-end design flow is processed using Xilinx Vivado System Design Suite software tools and target verification is done by using Artix 7 FPGA. Virtual I/O concept is used for the verification process. It will perform 32 different operations including parity generation and code conversions: Binary to Grey and Grey to Binary. It is a low power design implemented with Verilog HDL and power analysis is implementedwith clock frequencies ranging from 10MhZ to 100GhZ. With all these frequencies, power analysis is verified for different I/O standards LVCMOS12, LVCMOS25 and LVCMOS33.  

scholarly journals Web-Based Simulation Environment for Vehicular Electrical Networks

Energies ◽  
2021 ◽  
Vol 14 (19) ◽  
pp. 6087
Author(s):  
Xavier Dominguez ◽  
Paola Mantilla-Pérez ◽  
Nuria Gimenez ◽  
Islam El-Sayed ◽  
Manuel Alberto Díaz Díaz Millán ◽  
...  
Keyword(s):  
Visual Analytics ◽  
Distribution Systems ◽  
Software Tool ◽  
Automatic Generation ◽  
Electrical Networks ◽  
Web Based ◽  
Electrical Distribution Systems ◽  
Technical Requirements ◽  
Information Interaction

For the validation of vehicular Electrical Distribution Systems (EDS), engineers are currently required to analyze disperse information regarding technical requirements, standards and datasheets. Moreover, an enormous effort takes place to elaborate testing plans that are representative for most EDS possible configurations. These experiments are followed by laborious data analysis. To diminish this workload and the need for physical resources, this work reports a simulation platform that centralizes the tasks for testing different EDS configurations and assists the early detection of inadequacies in the design process. A specific procedure is provided to develop a software tool intended for this aim. Moreover, the described functionalities are exemplified considering as a case study the main wire harness from a commercial vehicle. A web-based architecture has been employed in alignment with the ongoing software development revolution and thus provides flexibility for both, developers and users. Due to its scalability, the proposed software scheme can be extended to other web-based simulation applications. Furthermore, the automatic generation of electrical layouts for EDS is addressed to favor an intuitive understanding of the network. To favor human–information interaction, utilized visual analytics strategies are also discussed. Finally, full simulation workflows are exposed to provide further insights on the deployment of this type of computer platforms.

Riser Response Based Optimal Positioning of Deep-Water Vessels

2005 ◽  
Author(s):  
Christopher Hoen
Keyword(s):  
Dynamic Response ◽  
Deep Water ◽  
Attractive Alternative ◽  
Practical Applications ◽  
Regression Curves ◽  
Coiled Tubing ◽  
Transverse Current ◽  
Open Sea ◽  
Slow Drift ◽  
On Line

The present paper discusses the mathematical modeling of risers and riser-like structures applied in a positioning context for deep-water floating vessels. The main purpose of the paper is to show that an estimate for the optimal vessel position, sufficient for most practical applications, is obtained from measurements of the riser inclinations or related parameters at lower end, and optionally upper end, through a solution based on the variably tensioned beam differential equation. Due to the ease of implementation this solution is well suited for direct application in on-line riser monitoring systems. The method is an attractive alternative to on-line FE-analyses, application of pre-computed regression curves based on idealized loading or black-box neural networks, which has been proposed by others to be applied as basis for interpretation of the measured riser responses. The basic idea behind the method is based on the observation that the riser inclinations or stress-joint moments at upper and lower end have mainly two causes. Firstly an effect caused by the position of the riser top end relative to the wellhead due to permanent vessel offset and slow drift vessel motions, and secondly the effects of transverse current down the riser. The general theory behind the method will be outlined. It will then be shown how the method adapts to drilling-risers with flex-joints, risers with stress-joints and also to the special case of well intervention with coiled tubing in open sea without applying a work-over or marine riser. The performance of the method is illustrated using simulated vessel and riser dynamic response data. The simulations are performed for selected vessel types both for deep-water and shallower waters applying state-of-the-art software for simulation of the riser and vessel dynamic response in random sea states.

scholarly journals Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller

Electronics ◽  
2019 ◽  
Vol 8 (5) ◽  
pp. 482
Author(s):  
Mangi Han ◽  
Youngmin Kim
Keyword(s):  
High Performance ◽  
Electronic Device ◽  
Finite Impulse Response ◽  
Parallel Implementation ◽  
Power Level ◽  
Digital Signal ◽  
Digital Circuit ◽  
Output Power Level ◽  
Verilog Hdl ◽  
Field Programmable

In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

Hands-On DSP Education through Experiments

2012 ◽  
Vol 49 (3) ◽  
pp. 302-309 ◽  
Author(s):  
Rifat Benveniste ◽  
Cem Ünsalan
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Engineering Education ◽  
Real Time ◽  
Digital Signal ◽  
Practical Applications ◽  
Hands On ◽  
New Graduate ◽  
Electrical Engineering Education ◽  
Secure Place

A new graduate from electrical engineering education must know about digital signal processing (DSP) to find a secure place in the competitive jobs market. Although this topic can be taught theoretically, its importance comes from practical applications. Therefore, students must be equipped with appropriate tools. Fortunately, DSP platforms serve this purpose. At Yeditepe University, we established a laboratory to guide students in real-time digital signal processing applications. We selected a Texas Instruments TMS320C6713 DSK platform for this purpose. In this study, we provide several laboratory applications on this platform. We also provide more advanced projects developed by our students which emerged from these applications. We observed that this laboratory improved the understanding of theoretical DSP concepts.

EDUCATIONAL PLATFORM FOR REAL-TIME DIGITAL SIGNAL PROCESSING: PRACTICAL APPLICATIONS OF DIGITAL FILTERS

2017 ◽  
Vol 36 (1) ◽  
Author(s):  
Wesley Becari ◽  
Rodrigo B. dos Santos ◽  
André B. Carlos ◽  
Rafael A. Biliatto ◽  
Henrique E. M. Peres
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Real Time ◽  
Digital Filters ◽  
Digital Signal ◽  
Practical Applications

scholarly journals Stepwise Transformation of Algorithms into Array Processor Architectures by the DECOMP

VLSI Design ◽  
1995 ◽  
Vol 3 (1) ◽  
pp. 67-80
Author(s):  
Uwe Vehlies
Keyword(s):  
Digital Signal ◽  
Design Flow ◽  
Array Processor ◽  
Formal Approach ◽  
Processor Architectures ◽  
Massively Parallel Systems ◽  
Signal Processing Algorithms ◽  
Hardware Description ◽  
High Level ◽  
Short Time

A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for array processor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.

scholarly journals A method to reduce ambiguities of qualitative reasoning for conceptual design applications

2013 ◽  
Vol 27 (1) ◽  
pp. 19-35
Author(s):  
Valentina D'Amelio ◽  
Magdalena K. Chmarra ◽  
Tetsuo Tomiyama
Keyword(s):  
Qualitative Methods ◽  
Conceptual Design ◽  
Software Tool ◽  
Quantitative Information ◽  
Qualitative Reasoning ◽  
Interaction Method ◽  
Research Results ◽  
Practical Applications ◽  
New Feature ◽  
Knowledge Intensive

AbstractQualitative reasoning can generate ambiguous behaviors due to the lack of quantitative information. Despite many different research results focusing on ambiguities reduction, fundamentally it is impossible to totally remove ambiguities with only qualitative methods and to guarantee the consistency of results. This prevents the wide use of qualitative reasoning techniques in practical situations, particularly in conceptual design, where qualitative reasoning is considered intrinsically useful. To improve this situation, this paper initially investigates the origin of ambiguities in qualitative reasoning. Then it proposes a method based on intelligent interventions of the user who is able to detect ambiguities, to prioritize interventions on these ambiguities, and to reduce ambiguities based on the least commitment strategy. This interaction method breaks through the limit of qualitative reasoning in practical applications to conceptual design. The method was implemented as a new feature in a software tool called the Knowledge Intensive Engineering Framework in order to be tested and used for a printer design.

scholarly journals An Efficient MAC Architecture using Multiplier for DSP and DIP Operations

2018 ◽  
Vol 7 (2.16) ◽  
pp. 110
Author(s):  
P Rahul Reddy ◽  
Pandya Vyomal N ◽  
Abhishek Choubey
Keyword(s):  
Signal Processing ◽  
Hearing Aids ◽  
High Performance ◽  
Digital Signal ◽  
Building Blocks ◽  
Hardware Architecture ◽  
Verilog Hdl ◽  
Medical Discipline ◽  
Critical Components ◽  
Wallace Tree Multiplier

DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors.  These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.

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