scholarly journals Simulating of charge build-up in irradiated MOS/SOI transistors

Author(s):  
D. A. Ogorodnikov ◽  
S. B. Lastovskii ◽  
Yu. V. Bogatyrev

The charge build-up in the interface of silicon / buried oxide in n-channel MOS/SOI transistors depending on their geometric parameters and electrical modes during ionizing irradiation is calculated with the use of the software Silvaco. It is shown that the electrical mode is most “harsh”, when during irradiation the voltage of +5 V is applied to drain and source electrodes and 0 V is applied to substrate, gate and channel feeding. The amount of the built-up charge can be substantially reduced by applying a negative bias to the substrate and by decreasing the thickness of the buried oxide layer.

1985 ◽  
Vol 53 ◽  
Author(s):  
S.J. Krause ◽  
C.O. Jung ◽  
S.R. Wilson ◽  
R.P. Lorigan ◽  
M.E. Burnham

ABSTRACTOxygen has been implanted into Si wafers at high doses and elevated temperatures to form a buried SiO2 layer for use in silicon-on-insulator (SOI) structures. Substrate heater temperatures have been varied (300, 400, 450 and 500°C) to determine the effect on the structure of the superficial Si layer through a processing cycle of implantation, annealing, and epitaxial growth. Transmission electron microscopy was used to characterize the structure of the superficial layer. The structure of the samples was examined after implantation, after annealing at 1150°C for 3 hours, and after growth of the epitaxial Si layer. There was a marked effect on the structure of the superficial Si layer due to varying substrate heater temperature during implantation. The single crystal structure of the superficial Si layer was preserved at all implantation temperatures from 300 to 500°C. At the highest heater temperature the superficial Si layer contained larger precipitates and fewer defects than did wafers implanted at lower temperatures. Annealing of the as-implanted wafers significantly reduced structural differences. All wafers had a region of large, amorphous 10 to 50 nm precipitates in the lower two-thirds of the superficial Si layer while in the upper third of the layer there were a few threading dislocations. In wafers implanted at lower temperatures the buried oxide grew at the top surface only. During epitaxial Si growth the buried oxide layer thinned and the precipitate region above and below the oxide layer thickened for all wafers. There were no significant structural differences of the epitaxial Si layer for wafers with different implantation temperatures. The epitaxial layer was high quality single crystal Si and contained a few threading dislocations. Overall, structural differences in the epitaxial Si layer due to differences in implantation temperature were minimal.


2011 ◽  
Vol 26 (9) ◽  
pp. 095005 ◽  
Author(s):  
S E Jamali Mahabadi ◽  
Ali A Orouji ◽  
P Keshavarzi ◽  
Hamid Amini Moghadam

2007 ◽  
Vol 84 (9-10) ◽  
pp. 2129-2132
Author(s):  
V. Tsouti ◽  
G. Papaioannou ◽  
J. Jomaah ◽  
F. Balestra
Keyword(s):  

Author(s):  
S. I. Romanov ◽  
A. V. Dvurechenskii ◽  
Yu. I. Yakovlev ◽  
R. Grötzschel ◽  
U. Kreissig ◽  
...  

1994 ◽  
Author(s):  
A. Y. Gasilov ◽  
Alexander N. Magunov ◽  
M. I. Makovijchuk ◽  
Evgenii O. Parshin

1997 ◽  
Vol T69 ◽  
pp. 341-344
Author(s):  
Chong-Man Yun ◽  
Jae-Hyung Kim ◽  
Min-Koo Han ◽  
Yearn-Ik Choi
Keyword(s):  

2020 ◽  
Vol 29 (2) ◽  
pp. 028501
Author(s):  
Xian-Cheng Liu ◽  
Jia-Jun Ma ◽  
Hong-Yun Xie ◽  
Pei Ma ◽  
Liang Chen ◽  
...  
Keyword(s):  

1994 ◽  
Vol 141 (10) ◽  
pp. 2801-2804 ◽  
Author(s):  
V. V. Afanas'ev ◽  
A. G. Revesz ◽  
G. A. Brown ◽  
H. L. Hughes

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