X-ray characterization of BUSARD chip: A HV-SOI monolithic particle detector with pixel sensors under the buried oxide

This work presents the design of BUSARD, an application specific integrated circuit (ASIC) for the detection of ionizing particles. The ASIC is a monolithic active pixel sensor which has been fabricated in a High-Voltage Silicon-On-Insulator (HV-SOI) process that allows the fabrication of a buried N+ diffusion below the Buried OXide (BOX) as a standard processing step. The first version of the chip, BUSARD-A, takes advantage of this buried diffusion as an ionizing particle sensor. It includes a small array of 13×13 pixels, with a pitch of 80 μm, and each pixel has one buried diffusion with a charge amplifier, discriminator with offset tuning and digital processing. The detector has several operation modes including particle counting and Time-over-Threshold (ToT). An initial X-ray characterization of the detector was carried out, obtaining several pulse height and ToT spectra, which then were used to perform the energy calibration of the device. The Molybdenum 𝐊α emission was measured with a standard deviation of 127 e- of ENC by using the analog pulse output, and with 276 e- of ENC by using the ToT digital output. The resolution in ToT mode is dominated by the pixel-to-pixel variation.

Ground plane and selective buried oxide based planar junctionless transistor

In this work, we demonstrate a ground plane (GP) based Selective Buried Oxide (SELBOX) Junctionless Transistor (JLT), named as GP-SELBOX-JLT. The use of GP and SELBOX in the proposed device reduces the electric field and enhances volume depletion in the channel, hence improves I ON/I OFF ratio and scalability. Using calibrated 2-D simulation, we have shown that proposed device exhibits better Short Channel Effect (SHE) immunity as compared to SOI-JLT. Therefore, the proposed GP-SELBOX-JLT can be scaled without degrading the performance in sub 20 nm regime. In addition, the ac study has shown that the cutoff frequency (f T) of GP-SELBOX-JLT is almost equal to conventional SOI-JLT.

Π-Shape Silicon Window for Controlling OFF-Current in Junctionless SOI MOSFET

in this paper a modified junctionless transistor is proposed. The aim of the novel structure is controlling off-current using π-shape silicon window in the buried oxide under the source and the channel regions. The π-shape window changes the potential profile in the channel region in which the conduction band energy get away from the body Fermi energy and rebuild an electrostatic potential. Beside the significant reduced off-current, on current has acceptable value in the novel Silicon Region Junctionless MOSFET (SR-JMOSFET) than Conventional Junctionless MOSFET (C-JMOSFET). Moreover, replacing silicon material instead of silicon dioxide in the buried oxide causes reduced maximum temperature in the channel region. In this situation the heat could transfer to the π-shape silicon window and the temperature reduces in the active region, significantly.The simulation with the two-dimensional ATLAS simulator shows that short channel effects such as subthreshold and DIBL are controlled effectively in the SR-JMOSFET. Also, the optimum values of length and thickness of the π-shape window are defined to obtain the best behavior of the device.

New 4H-SiC Metal Semiconductor Field Effect Transistors with Double Symmetric Step Buried Oxide Layer for High Energy Efficiency Applications

A novel 4H-SiC metal semiconductor field effect transistor (MESFET) device with double symmetric step buried oxide layer is proposed and the mechanism is studied through TCAD simulation. The step buried oxide layer is mainly to reduce the current leakage to the substrate and improve drain current. At the same time, the presence of the oxide layer changes the electric field distribution, reduces the electric field concentration phenomenon, and the breakdown voltage is improved. Due to the presence of the step buried oxide layer, the charge distribution of the device is changed, and the frequency characteristics are improved. When the step buried oxide channel is under the optimized parameter condition, compared with the traditional double-recessed structure 4H-SiC MESFET (DR 4H-SiC MESFET), the direct current (DC) characteristics of the new structure are improved, and the breakdown voltage is increased by 14% to reach 183 V. In radio frequency (RF) characteristics, cut-off frequency is 24.4 GHz, an increase of 11.9 %; maximum operating frequency is 63.9 GHz, an increase of 20.3%; the maximum power added efficiency (PAE) in the L-band and S-band reaches 63.5 %, PAE is 23.7 % higher than the DR structure. At the end of this paper, the new structure is verified for high-energy-efficiency, and the results show that the new structure has great potential in high-frequency applications.

Photonics Rib Waveguide Dimension Dependent Charge Distribution and Loss Characterization

The simulation of behaviour of the charge distribution and the loss characteristic for rib-waveguide is demonstrated by using silicon-on-insulator (SOI). In this simulation, the rib waveguide is designed at a core width of 450nm, core height of 250nm, rib height of 50nm and buried oxide height of 100nm. These dimensions are set as reference. The aspiration of designing rib waveguide instead of other type of waveguide such as ridge waveguide is from the higher light confinement that can be accomplished by rib waveguide as the refractive index difference is huge and the designing of an active device can be realized. In this analysis, free carrier-injection effect was implemented in the first part of the simulation to study the distribution charges of rib-based waveguide structure based on basic dimensions. In this analysis, electrical voltage was varied from 0V to 1.2V in steps of 0.2V for the analysis of distribution of electron. In the second part of the simulation, four design parameters had been amended which included the core width and height, rib height and buried oxide height. Physical dimensions of the waveguide were altered to achieve smaller device footprint with optimized performance affecting large Free Spectral Range (FSR) and high Q-factor. With proper waveguide physical dimensions design, a good performance Micro-Ring Resonator (MRR) exhibits the principles of wide FSR and Q-factor can be achieved.