A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

2011 ◽  
Vol 26 (9) ◽  
pp. 095005 ◽  
Author(s):  
S E Jamali Mahabadi ◽  
Ali A Orouji ◽  
P Keshavarzi ◽  
Hamid Amini Moghadam
2012 ◽  
Vol 236-237 ◽  
pp. 797-800
Author(s):  
Xiao Ming Yang ◽  
Yu Cai ◽  
Tian Qian Li

A slope SOI-LDMOS power device is proposed for high-voltage. When a positive bais is applied to the drain electrode, holes are induced and astricted by the slope buried oxide layer. So a high density positive charge layer is formed on the buried oxide layer. The electrical field in the buried oxide is improved as well as vertical breakdown voltage by the layer. Because the thickness of the drift region linearly increases from the source to the drain, the surface electric field is optimized, resulting in increase of lateral breakdown voltage. In this paper, the electric characteristics of the new device are simulated by Medici softerware. The result is shown that above 600 V breakdown voltage is obtained at 1μm thick buried oxide layer. The breakdown voltage is higher by three times than that of conventional SOI LDMOS.


2021 ◽  
Author(s):  
Shunwei Zhu ◽  
Hujun Jia ◽  
Mengyu Dong ◽  
Xiaowei Wang ◽  
Yintang Yang

Abstract A novel 4H-SiC metal semiconductor field effect transistor (MESFET) device with double symmetric step buried oxide layer is proposed and the mechanism is studied through TCAD simulation. The step buried oxide layer is mainly to reduce the current leakage to the substrate and improve drain current. At the same time, the presence of the oxide layer changes the electric field distribution, reduces the electric field concentration phenomenon, and the breakdown voltage is improved. Due to the presence of the step buried oxide layer, the charge distribution of the device is changed, and the frequency characteristics are improved. When the step buried oxide channel is under the optimized parameter condition, compared with the traditional double-recessed structure 4H-SiC MESFET (DR 4H-SiC MESFET), the direct current (DC) characteristics of the new structure are improved, and the breakdown voltage is increased by 14% to reach 183 V. In radio frequency (RF) characteristics, cut-off frequency is 24.4 GHz, an increase of 11.9 %; maximum operating frequency is 63.9 GHz, an increase of 20.3%; the maximum power added efficiency (PAE) in the L-band and S-band reaches 63.5 %, PAE is 23.7 % higher than the DR structure. At the end of this paper, the new structure is verified for high-energy-efficiency, and the results show that the new structure has great potential in high-frequency applications.


1985 ◽  
Vol 53 ◽  
Author(s):  
S.J. Krause ◽  
C.O. Jung ◽  
S.R. Wilson ◽  
R.P. Lorigan ◽  
M.E. Burnham

ABSTRACTOxygen has been implanted into Si wafers at high doses and elevated temperatures to form a buried SiO2 layer for use in silicon-on-insulator (SOI) structures. Substrate heater temperatures have been varied (300, 400, 450 and 500°C) to determine the effect on the structure of the superficial Si layer through a processing cycle of implantation, annealing, and epitaxial growth. Transmission electron microscopy was used to characterize the structure of the superficial layer. The structure of the samples was examined after implantation, after annealing at 1150°C for 3 hours, and after growth of the epitaxial Si layer. There was a marked effect on the structure of the superficial Si layer due to varying substrate heater temperature during implantation. The single crystal structure of the superficial Si layer was preserved at all implantation temperatures from 300 to 500°C. At the highest heater temperature the superficial Si layer contained larger precipitates and fewer defects than did wafers implanted at lower temperatures. Annealing of the as-implanted wafers significantly reduced structural differences. All wafers had a region of large, amorphous 10 to 50 nm precipitates in the lower two-thirds of the superficial Si layer while in the upper third of the layer there were a few threading dislocations. In wafers implanted at lower temperatures the buried oxide grew at the top surface only. During epitaxial Si growth the buried oxide layer thinned and the precipitate region above and below the oxide layer thickened for all wafers. There were no significant structural differences of the epitaxial Si layer for wafers with different implantation temperatures. The epitaxial layer was high quality single crystal Si and contained a few threading dislocations. Overall, structural differences in the epitaxial Si layer due to differences in implantation temperature were minimal.


2007 ◽  
Vol 84 (9-10) ◽  
pp. 2129-2132
Author(s):  
V. Tsouti ◽  
G. Papaioannou ◽  
J. Jomaah ◽  
F. Balestra
Keyword(s):  

Author(s):  
S. I. Romanov ◽  
A. V. Dvurechenskii ◽  
Yu. I. Yakovlev ◽  
R. Grötzschel ◽  
U. Kreissig ◽  
...  

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