Detecting GNSS Spoofing using Temporal Behavior of Spoofed Signals

2021 ◽  
Author(s):  
Birendra Kujur ◽  
Samer Khanafseh ◽  
Boris Pervan
Keyword(s):  
2004 ◽  
Vol 91 (5) ◽  
pp. 2051-2065 ◽  
Author(s):  
Dries H. G. Louage ◽  
Marcel van der Heijden ◽  
Philip X. Joris

Temporal information in the responses of auditory neurons to sustained sounds has been studied mostly with periodic stimuli, using measures that are based on Fourier analysis. Less information is available on temporal aspects of responses to nonperiodic wideband sounds. We recorded responses to a reference Gaussian noise and its polarity-inverted version in the auditory nerve of barbiturate-anesthetized cats and used shuffled autocorrelograms (SACs) to quantify spike timing. Two metrics were extracted from the central peak of autocorrelograms: the peak-height and the width at halfheight. Temporal information related to stimulus fine-structure was isolated from that to envelope by subtracting or adding responses to the reference and inverted noise. Peak-height and halfwidth generally behaved as expected from the existing body of data on phase-locking to pure tones and sinusoidally amplitude-modulated tones but showed some surprises as well. Compared with synchronization to low-frequency tones, SACs reveal large differences in temporal behavior between the different classes of nerve fibers (based on spontaneous rate) as well as a strong dependence on characteristic frequency (CF) throughout the phase-locking range. SACs also reveal a larger temporal consistency (i.e., tendency to discharge at the same point in time on repeated presentation of the same stimulus) in the responses to the stochastic noise stimulus than in the responses to periodic tones. Responses at high CFs reflect envelope phase-locking and are consistent with previous reports using sinusoidal AM. We conclude that the combined use of broadband noise and SAC analysis allow a more general characterization of temporal behavior than periodic stimuli and Fourier analysis.


2006 ◽  
Vol 119-120 ◽  
pp. 33-37 ◽  
Author(s):  
Y. Kagotani ◽  
K. Miyajima ◽  
S. Saito ◽  
M. Ashida ◽  
T. Itoh

1998 ◽  
Vol 7 (6) ◽  
pp. 443-450
Author(s):  
Sun Xiu-dong ◽  
Feng Yu-wen ◽  
Jiang Yong-yuan ◽  
Li Yan ◽  
Zhou Zhong-xiang

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 69-80 ◽  
Author(s):  
Anand V. Hudli ◽  
Raghu V. Hudli

Test generation for sequential VLSI circuits has remained a difficult problem to solve. The difficulty arises because of reasoning about temporal behavior of sequential circuits. We use temporal logic to model digital circuits. Temporal Logic can model circuits hierarchically. A set of heuristics is given to aid during test generation. A hierarchical test generation algorithm is proposed.


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