A Reference-Sampling Based Calibration-Free Fractional-N PLL with A PI-Linked Sampling Clock Generator

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

A High-Speed Programmable Frequency Divider for a Ka-Band Phase Locked Loop-Type Frequency Synthesizer in 90-nm CMOS

A high-speed programmable frequency divider for a Ka-band phase-locked loop (PLL)-type frequency synthesizer system is presented and fabricated in 90 nm CMOS technology. It consists mainly of a divided-by-8/9 dual-modulus prescaler (DMP) and pulse swallow counters. An active-inductor-based source-coupled logic (SCL) D flip-flop (DFF) and the “OR” gate are used in the DMP in order to promote its locking range and operation frequency. The measured operation frequency range of the improved programmable frequency divider covers from 6 to 20 GHz with a low phase noise of less than −136 dBc/Hz at a 1 MHz offset of output signals, an optimum sensitivity of −27 dBm at 15 GHz, and a low power consumption of 9.1 mW.

Modulation Performance Enhancement of Directly Modulated Injection-Locked Semiconductor Lasers Using an Equivalent Electrical Circuit

We propose an equivalent electrical circuit model to evaluate the direct modulation performance of optically injection-locked (OIL) semiconductor lasers. We modeled the equivalent circuit of the OIL laser based on alternating complex envelope representations, simulated it using the Simulation Program with Integrated Circuit Emphasis (SPICE), and analyzed the frequency response of the OIL laser. Although the frequency response of the OIL laser is better than that of a free-running laser, its 3-dB modulation performance is degraded by the relaxation oscillation that occurs during direct modulation of the semiconductor laser. To overcome this limitation and maintain the maximum modulation performance within the entire locking range, we also designed an electrical filter to preprocess the electrical modulation signal and compensate for the non-flat modulation output of the OIL laser. The damping ratio of the directly modulated OIL laser increased by 0.101 (280%) and its settling time decreased by >0.037 (44%) when the electrical compensation circuit was added, exhibiting a flat 3-dB modulation bandwidth of 28.79 GHz.

Stabilizing nanolasers via polarization lifetime tuning

We investigate the emission dynamics of mutually coupled nanolasers and predict ways to optimize their stability, i.e., maximize their locking range. We find that tuning the cavity lifetime to the same order of magnitude as the dephasing time of the microscopic polarization yields optimal operation conditions, which allow for wider tuning ranges than usually observed in conventional semiconductor lasers. The lasers are modeled by Maxwell–Bloch type class-C equations. For our analysis, we analytically determine the steady state solutions, analyze the symmetries of the system and numerically characterize the emission dynamics via the underlying bifurcation structure. The polarization lifetime is found to be a crucial parameter, which impacts the observed dynamics in the parameter space spanned by frequency detuning, coupling strength and coupling phase.

Stabilizing Nanolasers via Polarization Lifetime Tuning

We investigate the emission dynamics of mutually coupled nanolasers and predict ways to optimize their stability i.e. maximize their locking range. We find that tuning the cavity lifetime to the same order of magnitude as the dephasing time of the microscopic polarization yields optimal operation conditions which allow for wider tuning ranges than usually observed in conventional semiconductor lasers. The lasers are modeled by a Maxwell-Bloch type class-C laser model. For our analysis we analytically determine the steady state solutions, analyze the symmetries of the system and numerically characterize the emission dynamics via the underlying bifurcation structure. The polarization lifetime is found to be a crucial parameter which impacts the observed dynamics in the parameter space spanned by frequency detuning, coupling strength and coupling phase.

Circuits and architectures for high frequency synthesizer in CMOS

This thesis proposes a novel architecture for high frequency synthesizer design focusing mainly on the 60 GHz frequency range. It consists of a PLL cascaded to an ILO. In order to generate narrow pulses and to relax the multiplication ration of the ILO, a DLL with a pulse generator is used. Passive delay line stacked on top of LC VCO is used for power efficiency and replica-biasing technique of frequency tracking is used for increasing the locking range of ILO. The synthesizer operates at 50 GHz with a phase noise of -98, -117 and -128 dBc/Hz at 1 MHz, 10 MHz and 40 MHz respectively. The total power consumed by the frequency synthesizer from 1.2 V supply is 57 mW. To have channel selection capability, fractional PLL may be used. A novel fractional PLL architecture is also proposed which de-couples the residual jitter from the PLL bandwidth.

Circuits and architectures for high frequency synthesizer in CMOS

This thesis proposes a novel architecture for high frequency synthesizer design focusing mainly on the 60 GHz frequency range. It consists of a PLL cascaded to an ILO. In order to generate narrow pulses and to relax the multiplication ration of the ILO, a DLL with a pulse generator is used. Passive delay line stacked on top of LC VCO is used for power efficiency and replica-biasing technique of frequency tracking is used for increasing the locking range of ILO. The synthesizer operates at 50 GHz with a phase noise of -98, -117 and -128 dBc/Hz at 1 MHz, 10 MHz and 40 MHz respectively. The total power consumed by the frequency synthesizer from 1.2 V supply is 57 mW. To have channel selection capability, fractional PLL may be used. A novel fractional PLL architecture is also proposed which de-couples the residual jitter from the PLL bandwidth.

A 17.8–34.8 GHz (64.6%) Locking Range Current-Reuse Injection-Locked Frequency Multiplier with Dual Injection Technique

A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is proposed to reduce the power consumption and compatibility with NMOS and PMOS injectors. The inductor-capacitor (LC) tank of the proposed CR-ILFM is designed with a fourth-order resonator using a transformer with distributed inductor to extend the locking range. The self-oscillated frequency of the proposed CR-ILFM is 23.82 GHz. The output frequency locking range is 17.8–34.8 GHz (64.6%) at a 0-dBm injection power without any additional control including supply voltage, varactor, and capacitor bank. The power consumption of the proposed CR-ILFM is 7.48 mW from a 1-V supply voltage and the die size is 0.75 mm × 0.45 mm. The CR-ILFM is implemented in a 65-nm CMOS technology.