Evaluation of Green Alternatives for Blockchain Proof-of-Work (PoW) Approach

2021 ◽  
Vol 5 (4) ◽  
pp. 54-59
Author(s):  
Mahdi H. Miraz ◽  
Peter S. Excell ◽  
Khan Sobayel

Following the footprints of Bitcoins, many other cryptocurrencies were developed mostly adopting the same or similar Proof-of-Work (PoW) approach. Since completing the PoW puzzle requires extremely high computing power, consuming a vast amount of electricity, PoW has been strongly criticised for its antithetic stand against the notion of green computing. Use of application-specific hardware, particularly application-specific integrated circuits (ASICs) has further fuelled the debate, as these devices are of no use once they become “legacy” and hence obsolete to compete in the mining race, thus contributing to electronics waste. Therefore, this paper surveys the currently available alternative approaches to PoW and evaluates their applicability - especially their appropriateness in terms of greenness.

MRS Bulletin ◽  
1993 ◽  
Vol 18 (6) ◽  
pp. 46-51 ◽  
Author(s):  
S.P. Murarka ◽  
J. Steigerwald ◽  
R.J. Gutmann

Continuing advances in the fields of very-large-scale integration (VLSI), ultralarge-scale integration (ULSI), and gigascale integration (GSI), leading to the continuing development of smaller and smaller devices, have continually challenged the fields of materials, processes, and circuit designs. The existing metallization schemes for ohmic contacts, gate metal, and interconnections are inadequate for the ULSI and GSI era. An added concern is the reliability of aluminum and its alloys as the current carrier. Also, the higher resistivity of Al and its use in two-dimensional networks have been considered inadequate, since they lead to unacceptably high values of the so-called interconnection delay or RC delay, especially in microprocessors and application-specific integrated circuits (ICs). Here, R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the RC delay must be reduced to such a level that the contribution of RC to switching delays (access time) becomes a small fraction of the total, which is a sum of the inherent device delay associated with the semiconductor, the device geometry and type, and the RC delay.


2021 ◽  
Author(s):  
Michael Mattioli

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>


2003 ◽  
Author(s):  
Steffen Chemnitz ◽  
Heiko Schafer ◽  
Stephanie Schumacher ◽  
Volodymyr Koziy ◽  
Alexander Fischer ◽  
...  

Author(s):  
Rajesh K. Karmani ◽  
Gul Agha ◽  
Mark S. Squillante ◽  
Joel Seiferas ◽  
Marian Brezina ◽  
...  

2010 ◽  
Vol 128 (4) ◽  
pp. 2381-2381
Author(s):  
Armando Jiménez Flores ◽  
Maximino Peña Guerrero ◽  
Jose J. Negrete Redondo

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