Eye State Identification Based on Discrete Wavelet Transforms

We present a prototype to identify eye states from electroencephalography signals captured from one or two channels. The hardware is based on the integration of low-cost components, while the signal processing algorithms combine discrete wavelet transform and linear discriminant analysis. We consider different parameters: nine different wavelets and two features extraction strategies. A set of experiments performed in real scenarios allows to compare the performance in order to determine a configuration with high accuracy and short response delay.

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Prediction of Small Drill Bit Breakage Using the Discrete Wavelet Transforms and Linear Discriminant Functions.

Journal of the Japan Society for Precision Engineering ◽

10.2493/jjspe.65.598 ◽

1999 ◽

Vol 65 (4) ◽

pp. 598-603

Author(s):

Nagayoshi KASASHIMA ◽

Kazuo MORI ◽

FU J.C. ◽

TROY C. ◽

Yoshihiro TAKEYASU

Keyword(s):

Wavelet Transforms ◽

Discrete Wavelet ◽

Discrete Wavelet Transforms ◽

Drill Bit ◽

Discriminant Functions ◽

Linear Discriminant

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Ultra-High Performance and Low-Cost Architecture of Discrete Wavelet Transforms

10.5772/intechopen.94858 ◽

2020 ◽

Author(s):

Mouhamad Chehaitly ◽

Mohamed Tabaa ◽

Fabrice Monteiro ◽

Safa Saadaoui ◽

Abbas Dandache

Keyword(s):

Wavelet Transforms ◽

High Speed ◽

High Performance ◽

Low Cost ◽

Discrete Wavelet ◽

Discrete Wavelet Transforms ◽

Depth Order ◽

Low Pass ◽

P 16 ◽

First And Second Generation

This work targets the challenging issue to produce high throughput and low-cost configurable architecture of Discrete wavelet transforms (DWT). More specifically, it proposes a new hardware architecture of the first and second generation of DWT using a modified multi-resolution tree. This approach is based on serializations and interleaving of data between different stages. The designed architecture is massively parallelized and sharing hardware between low-pass and high-pass filters in the wavelet transformation algorithm. Consequently, to process data in high speed and decrease hardware usage. The different steps of the post/pre-synthesis configurable algorithm are detailed in this paper. A modulization in VHDL at RTL level and implementation of the designed architecture on FPGA technology in a NexysVideo board (Artix 7 FPGA) are done in this work, where the performance, the configurability and the generic of our architecture are highly enhanced. The implementation results indicate that our proposed architectures provide a very high-speed data processing with low needed resources. As an example, with the parameters depth order equal 2, filter order equal 2, order quantization equal 5 and a parallel degree P = 16, we reach a bit rate around 3160 Mega samples per second with low used of logic elements ( ≈ 400) and logic registers ( ≈ 700 ).

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