Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions’ Pipelined Designs

High-throughput designs of hash functions are strongly demanded due to the need for security in every transmitted packet of worldwide e-transactions. Thus, optimized and non-optimized pipelined architectures have been proposed raising, however, important questions. Which is the optimum number of the pipeline stages? Is it worth to develop optimized designs or could the same results be achieved by increasing only the pipeline stages of the non-optimized designs? The paper answers the above questions studying extensively many pipelined architectures of SHA-1 and SHA-256 hashes, implemented in FPGAs, in terms of throughput/area (T/A) factor. Also, guides for developing efficient security schemes designs are provided.

A Generalized Frame-Level FSBM FLSA Architecture

Block-based motion estimation plays important roles in video applications such as video compression to detect movements as well as remove temporal redundancies between successive frames. Full-search block-matching (FSBM) is the preferred algorithm for accurate motion estimation. Frame-level pipelined systolic array (FLSA) FSBM architectures have advantages over block-level pipelined architectures in their simpler control and reduced number of memory accesses. In this paper, a frame-level pipelined FSBM motion estimation architecture using array processor for any square, N×N, block size is presented in full detail.