scholarly journals A Trellis Based Temporal Rate Allocation and Virtual Reference Frames for High Efficiency Video Coding

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1384
Author(s):  
Xiem HoangVan ◽  
Le Dao Thi Hue ◽  
Thuong Nguyen Canh

The High Efficiency Video Coding (HEVC) standard has now become the most popular video coding solution for video conferencing, broadcasting, and streaming. However, its compression performance is still a critical issue for adopting a large number of emerging video applications with higher spatial and temporal resolutions. To advance the current HEVC performance, we propose an efficient temporal rate allocation solution. The proposed method adaptively allocates the compression bitrate for each coded picture in a group of pictures by using a trellis-based dynamic programming approach. To achieve this task, we trained the trellis-based quantization parameter for each frame in a group of pictures considering the temporal layer position. We further improved coding efficiency by incorporating our proposed framework with other inter prediction methods such as a virtual reference frame. Experiments showed around 2% and 5% bitrate savings with our trellis-based rate allocation method with and without a virtual reference frame compared to the conventional HEVC standard, respectively.

2016 ◽  
Vol 11 (9) ◽  
pp. 764
Author(s):  
Lella Aicha Ayadi ◽  
Nihel Neji ◽  
Hassen Loukil ◽  
Mouhamed Ali Ben Ayed ◽  
Nouri Masmoudi

Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.


2021 ◽  
Vol 49 (4) ◽  
pp. 1013-1027
Author(s):  
Hajar Touzani ◽  
Anass Mansouri ◽  
Fatima Errahimi ◽  
Ali Ahaitouf

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