Compact differential signal balancer embedded in metal wiring layers of silicon LSI for common mode noise filtering

2020 ◽  
Vol 59 (SG) ◽  
pp. SGGC01
Author(s):  
Masaaki Kameya ◽  
Yang-Min Chang ◽  
Eishi Gofuku ◽  
Kazuyuki Nakamura
2009 ◽  
Vol 19 (1) ◽  
pp. 7-12
Author(s):  
Nikola Jorgovanovic ◽  
Dubravka Bojanic ◽  
Vojin Ilic ◽  
Darko Stanisic

We present the design, simulation and test results of a new AC amplifier for electrophysiological measurements based on a three op-amp instrumentation amplifier (IA). The design target was to increase the common mode rejection ratio (CMRR), thereby improving the quality of the recorded physiological signals in a noisy environment. The new amplifier actively suppresses the DC component of the differential signal and actively reduces the common mode signal in the first stage of the IA. These functions increase the dynamic range of the amplifier's first stage of the differential signal. The next step was the realization of the amplifier in a single chip technology. The design and tests of the new AC amplifier with a differential gain of 79.2 dB, a CMRR of 130 dB at 50 Hz, a high-pass cutoff frequency at 0.01 Hz and common mode reduction in the first stage of the 49.8 dB are presented in this paper.


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