scholarly journals Solution for the Problems in RADAR Systems from SNR Gain Expressions and Blackout Likelihood Detection for Aviation Systems

Issues confronted in Radar frameworks at SDSC are, It is exceptionally troublesome for them to track an flying machine and discover its point, run and rise. With the existing ACSs, being incapable to provide the required information capacity. Since this misfortune of communication takes put between the ground station to the discuss station, discuss crashes may happen. Thus to dodge these kind of issues, modern proposed framework is defined. The full Duplex and Half Duplex systems can be combined to form a Hybrid Duplex Systems (HBD-ACS). In the existing Half duplex system, there was a crux in the spectrum mainly in the aeronautical industry. Hence the new HBD-ACS in proposed which eliminates the progressive interference. Progressive interference detector includes two methods namely, expressions of SNR gain and blackout probability. The Full duplex system may consists of the leftover interference. Hence to eliminate this, Interference Ignorant detector and SIC detector are used. Hence from the HBD-ACS, the diversity gain will be non-zero and the interference can be limited.

2020 ◽  
Vol 65 (2) ◽  
pp. 1373-1384
Author(s):  
Xiaoye Shi ◽  
Jin Sun ◽  
Dongming Li ◽  
Fei Ding ◽  
Zhaowei Zhang

2015 ◽  
Vol 43 (1) ◽  
pp. 109-122 ◽  
Author(s):  
Jelena Marasevic ◽  
Jin Zhou ◽  
Harish Krishnaswamy ◽  
Yuan Zhong ◽  
Gil Zussman

IEEE Access ◽  
2017 ◽  
Vol 5 ◽  
pp. 7737-7745 ◽  
Author(s):  
Yurong Wang ◽  
Kui Xu ◽  
Aijun Liu ◽  
Xiaochen Xia
Keyword(s):  

2011 ◽  
Vol 383-390 ◽  
pp. 6840-6845 ◽  
Author(s):  
Yong Hong Gu ◽  
Wei Huang ◽  
Qiao Li Yang

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.


2018 ◽  
Vol 7 (2) ◽  
pp. 246-249 ◽  
Author(s):  
Alexandros-Apostolos A. Boulogeorgos ◽  
George K. Karagiannidis

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