FPGA Implementation of RECTANGLE Block Cipher Architectures

In recent time, various lightweight algorithms have been proposed to provide security in a constrained resource environment. With so many algorithms and their different implementations, it is hard to choose the appropriate security primitive for an application. In this work, various hardware implementations of lightweight block cipher RECTANGLE is proposed like Iterative design, 16-bits architecture, Reduced Substitution box design, RAM-based design and Iterative design with Partial loop unrolled. These designs provide aid in overcoming the problem of security in a constrained resource environment. Architectures are designed and implemented in various FPGA platforms. Results are extensively evaluated and compared on the basis of throughput, throughput/slice, area utilization, energy requirement and power consumption for their implementation in different FPGA platforms. Best trade-off among throughput and area is given by Iterative design with partial loop unrolling. It also gave best energy consumption values for all FPGAs. Ram-based design utilized least number of registers for its implementation.

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FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher

Sensors ◽

10.3390/s19040913 ◽

2019 ◽

Vol 19 (4) ◽

pp. 913 ◽

Cited By ~ 8

Author(s):

Sa’ed Abed ◽

Reem Jaffal ◽

Bassam Mohd ◽

Mohammad Alshayeji

Keyword(s):

Block Cipher ◽

Sensitive Data ◽

Hardware Implementations ◽

Balancing Energy ◽

Field Programmable ◽

Constrained Environments ◽

Continuous Stream ◽

Lightweight Block Cipher ◽

The One ◽

Least Area

Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.

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Compact Hardware Implementations of MISTY1 Block Cipher

Journal of Circuits System and Computers ◽

10.1142/s0218126618500378 ◽

2017 ◽

Vol 27 (03) ◽

pp. 1850037 ◽

Cited By ~ 3

Author(s):

Yasir ◽

Ning Wu ◽

Xiaoqiang Zhang

Keyword(s):

Low Power ◽

Block Cipher ◽

Comprehensive Analysis ◽

The Other ◽

Key Generation ◽

Round Function ◽

Other Hand ◽

Hardware Implementations ◽

Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

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Protecting lightweight block cipher implementation in mobile big data computing

Peer-to-Peer Networking and Applications ◽

10.1007/s12083-016-0481-0 ◽

2016 ◽

Vol 11 (2) ◽

pp. 252-264

Author(s):

Weidong Qiu ◽

Bozhong Liu ◽

Can Ge ◽

Lingzhi Xu ◽

Xiaoming Tang ◽

...

Keyword(s):

Big Data ◽

Block Cipher ◽

Mobile Big Data ◽

Lightweight Block Cipher ◽

Big Data Computing

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Eight-sided fortress: a lightweight block cipher

The Journal of China Universities of Posts and Telecommunications ◽

10.1016/s1005-8885(14)60275-2 ◽

2014 ◽

Vol 21 (1) ◽

pp. 104-128

Author(s):

Xuan LIU ◽

Wen-ying ZHANG ◽

Xiang-zhong LIU ◽

Feng LIU

Keyword(s):

Block Cipher ◽

Lightweight Block Cipher

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Optimization of Advanced Encryption Standard (AES) Using Vivado High Level Synthesis (HLS)

10.29007/x3tx ◽

2019 ◽

Author(s):

Luka Daoud ◽

Fady Hussein ◽

Nader Rafla

Keyword(s):

High Level Synthesis ◽

Advanced Encryption Standard ◽

Data Confidentiality ◽

Maximum Throughput ◽

Loop Unrolling ◽

Aes Algorithm ◽

Hardware Implementations ◽

High Level ◽

Dedicated Hardware ◽

Vivado Hls

Advanced Encryption Standard (AES) represents a fundamental building module of many network security protocols to ensure data confidentiality in various applications ranging from data servers to low-power hardware embedded systems. In order to optimize such hardware implementations, High-Level Synthesis (HLS) provides flexibility in designing and rapid optimization of dedicated hardware to meet the design constraints. In this paper, we present the implementation of AES encryption processor on FPGA using Xilinx Vivado HLS. The AES architecture was analyzed and designed by loop unrolling, and inner-round and outer-round pipelining techniques to achieve a maximum throughput of the AES algorithm up to 1290 Mbps (Mega bit per second) with very significant low resources of 3.24% slices of the FPGA, achieving 3 Mbps per slice area.

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