FPGA Modeling and Optimization of a SIMON Lightweight Block Cipher

Security of sensitive data exchanged between devices is essential. Low-resource devices (LRDs), designed for constrained environments, are increasingly becoming ubiquitous. Lightweight block ciphers provide confidentiality for LRDs by balancing the required security with minimal resource overhead. SIMON is a lightweight block cipher targeted for hardware implementations. The objective of this research is to implement, optimize, and model SIMON cipher design for LRDs, with an emphasis on energy and power, which are critical metrics for LRDs. Various implementations use field-programmable gate array (FPGA) technology. Two types of design implementations are examined: scalar and pipelined. Results show that scalar implementations require 39% less resources and 45% less power consumption. The pipelined implementations demonstrate 12 times the throughput and consume 31% less energy. Moreover, the most energy-efficient and optimum design is a two-round pipelined implementation, which consumes 31% of the best scalar’s implementation energy. The scalar design that consumes the least energy is a four-round implementation. The scalar design that uses the least area and power is the one-round implementation. Balancing energy and area, the two-round pipelined implementation is optimal for a continuous stream of data. One-round and two-round scalar implementations are recommended for intermittent data applications.

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A Novel Lightweight Block Cipher-Based Mutual Authentication Protocol for Constrained Environments

IEEE Access ◽

10.1109/access.2020.3021701 ◽

2020 ◽

Vol 8 ◽

pp. 165536-165550 ◽

Cited By ~ 1

Author(s):

Cuong Trinh ◽

Bao Huynh ◽

Jan Lansky ◽

Stanislava Mildeova ◽

Masoumeh Safkhani ◽

...

Keyword(s):

Block Cipher ◽

Mutual Authentication ◽

Authentication Protocol ◽

Constrained Environments ◽

Lightweight Block Cipher ◽

Mutual Authentication Protocol

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Integral Distinguishers of the Full-Round Lightweight Block Cipher SAT_Jo

Security and Communication Networks ◽

10.1155/2021/5310545 ◽

2021 ◽

Vol 2021 ◽

pp. 1-9

Author(s):

Xueying Qiu ◽

Yongzhuang Wei ◽

Samir Hodzic ◽

Enes Pasalic

Keyword(s):

Linear Programming ◽

Integer Linear Programming ◽

Mixed Integer Linear Programming ◽

Time Complexity ◽

Block Cipher ◽

Security Analysis ◽

Mixed Integer ◽

Substitution Boxes ◽

Lightweight Block Cipher ◽

The One

Integral cryptanalysis based on division property is a powerful cryptanalytic method whose range of successful applications was recently extended through the use of Mixed-Integer Linear Programming (MILP). Although this technique was demonstrated to be efficient in specifying distinguishers of reduced round versions of several families of lightweight block ciphers (such as SIMON, PRESENT, and few others), we show that this method provides distinguishers for a full-round block cipher SAT_Jo. SAT_Jo cipher is very similar to the well-known PRESENT block cipher, which has successfully withstood the known cryptanalytic methods. The main difference compared to PRESENT, which turns out to induce severe weaknesses of SAT_Jo algorithm, is its different choice of substitution boxes (S-boxes) and the bit-permutation layer for the reasons of making the cipher highly resource-efficient. Even though the designers provided a security analysis of this scheme against some major generic cryptanalytic methods, an application of the bit-division property in combination with MILP was not considered. By specifying integral distinguishers for the full-round SAT_Jo algorithm using this method, we essentially disapprove its use in intended applications. Using a 30-round distinguisher, we also describe a subkey recovery attack on the SAT_Jo algorithm whose time complexity is about 2 66 encryptions (noting that SAT_Jo is designed to provide 80 bits of security). Moreover, it seems that the choice of bit-permutation induces weak division properties since replacing the original bit-permutation of SAT_Jo by the one used in PRESENT immediately renders integral distinguishers inefficient.

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AN FPGA IMPLEMENTATION OF THE GPRS ENCRYPTION ALGORITHM 3 (GEA3)

Journal of Circuits System and Computers ◽

10.1142/s0218126605002337 ◽

2005 ◽

Vol 14 (02) ◽

pp. 217-231 ◽

Cited By ~ 5

Author(s):

P. KITSOS ◽

M. D. GALANIS ◽

O. KOUFOPAVLOU

Keyword(s):

Hardware Implementation ◽

Block Cipher ◽

Data Encryption ◽

Encryption Algorithm ◽

General Packet Radio Service ◽

Silicon Area ◽

Double Edge ◽

Hardware Implementations ◽

Field Programmable ◽

Significant Performance

The General Packet Radio Service (GPRS) uses the GPRS Encryption Algorithm 3 (GEA3) for data encryption. In this paper, alternative hardware implementations of the GEA3 algorithm are described. GEA3 algorithm is based on the KASUMI block cipher. Various KASUMI block cipher hardware implementations have been examined in order to provide information about the required silicon area and throughput. In order to achieve a significant performance improvement, Double Edge Triggered pipeline technique is used. The S-BOXes, which are fundamental elements of the KASUMI cipher, have been implemented by using combinational logic and ROM memories. The proposed GEA3 algorithm hardware implementation achieves throughput up to 837Mbps, which is much faster comparing to the previous designs. The whole system is implemented and evaluated by using Field Programmable Gate Array (FPGA) devices.

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FPGA Implementation of RECTANGLE Block Cipher Architectures

International Journal of Innovative Technology and Exploring Engineering - Special Issue ◽

10.35940/ijitee.g5481.0881019 ◽

2019 ◽

Vol 8 (10) ◽

pp. 2382-2391

Keyword(s):

Block Cipher ◽

Energy Requirement ◽

Recent Time ◽

Substitution Box ◽

Iterative Design ◽

Loop Unrolling ◽

Consumption Values ◽

Hardware Implementations ◽

Lightweight Block Cipher ◽

Resource Environment

In recent time, various lightweight algorithms have been proposed to provide security in a constrained resource environment. With so many algorithms and their different implementations, it is hard to choose the appropriate security primitive for an application. In this work, various hardware implementations of lightweight block cipher RECTANGLE is proposed like Iterative design, 16-bits architecture, Reduced Substitution box design, RAM-based design and Iterative design with Partial loop unrolled. These designs provide aid in overcoming the problem of security in a constrained resource environment. Architectures are designed and implemented in various FPGA platforms. Results are extensively evaluated and compared on the basis of throughput, throughput/slice, area utilization, energy requirement and power consumption for their implementation in different FPGA platforms. Best trade-off among throughput and area is given by Iterative design with partial loop unrolling. It also gave best energy consumption values for all FPGAs. Ram-based design utilized least number of registers for its implementation.

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Security Test by using F T M and Data Allocation Strategies on Leakage Detection

INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY ◽

10.24297/ijct.v4i2b1.3227 ◽

2005 ◽

Vol 4 (2) ◽

pp. 393-400

Author(s):

Pallavali Radha ◽

G. Sireesha

Keyword(s):

Third Party ◽

Distributed Data ◽

Data Allocation ◽

Security Testing ◽

Sensitive Data ◽

Sample Data ◽

The One ◽

Security Test ◽

Data Request ◽

Allocation Strategies

The data distributors work is to give sensitive data to a set of presumably trusted third party agents.The data i.e., sent to these third parties are available on the unauthorized places like web and or some ones systems, due to data leakage. The distributor must know the way the data was leaked from one or more agents instead of as opposed to having been independently gathered by other means. Our new proposal on data allocation strategies will improve the probability of identifying leakages along with Security attacks typically result from unintended behaviors or invalid inputs. Â Due to too many invalid inputs in the real world programs is labor intensive about security testing.The most desirable thing is to automate or partially automate security-testing process. In this paper we represented Predicate/ Transition nets approach for security tests automated generationby using formal threat models to detect the agents using allocation strategies without modifying the original data.The guilty agent is the one who leaks the distributed data. To detect guilty agents more effectively the idea is to distribute the data intelligently to agents based on sample data request and explicit data request. The fake object implementation algorithms will improve the distributor chance of detecting guilty agents.

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Compact Hardware Implementations of MISTY1 Block Cipher

Journal of Circuits System and Computers ◽

10.1142/s0218126618500378 ◽

2017 ◽

Vol 27 (03) ◽

pp. 1850037 ◽

Cited By ~ 3

Author(s):

Yasir ◽

Ning Wu ◽

Xiaoqiang Zhang

Keyword(s):

Low Power ◽

Block Cipher ◽

Comprehensive Analysis ◽

The Other ◽

Key Generation ◽

Round Function ◽

Other Hand ◽

Hardware Implementations ◽

Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

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