scholarly journals Parallelism Effects in Higher Term Dot Product Floating Point Computation

2020 ◽  
Vol 9 (1) ◽  
pp. 94-100
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Floating Point ◽  
Complex Signal ◽  
Accurate Representation ◽  
Dot Product ◽  
Floating Point Computation

In complex signal processing applications, Floating Point (FP) arithmetic is a complex, but extremely accurate representation, which needs to be optimizing by architectural modification. This paper describes discrete to fused arithmetic implementation with two, three and four operand FP methodology. Parameters like Area, Power and Delay (APD) are considered for analysis. Exhaustive analysis is carried out here from basic FP component to complete structuring of Four Term Dot Product FP (FTDPFP). Analysis shows that FTDPFP computation improves speed by 89-91% compared to three term and two term computation. Area wise overheads increases in FTDPFP and it is optimized by using new exponent, dual reduction, early normalization, Leading zero participator (LZA), rounding and compounding techniques. Power consumption is optimized with same competency of Two and Three Term Dot Product Floating Point (TTDPFP).

scholarly journals FIR Filter Design using Floating Point Column Bypassing Technique

2019 ◽  
Vol 8 (2S4) ◽  
pp. 409-413 ◽  
Keyword(s):  
Signal Processing ◽  
Power Consumption ◽  
Truncation Error ◽  
Filter Design ◽  
Fir Filter ◽  
Floating Point ◽  
Switching Activity ◽  
Software And Hardware ◽  
Fir Filter Design ◽  
Dsp Applications

This paper presents the design of floating point fixed-width multiplier using column bypassing technique for signal processing applications. The designed fixed-width multiplier provides less power consumption due to the reduction of switching activity in the operands of the partial products. This is the key element of the Multiply-accumulate (MAC) unit for enhancing its performance. The proposed MAC can be implemented in a FIR filter for DSP applications. To improve the accuracy of the FIR filter, various rounding methods have been used to solve the truncation error in the product. The power consumption is 10% lesser than conventional fixed-width multiplier and the accuracy also have been improved. The output response of the proposed filter will be simulated in the virtual software and hardware environment with the MATLAB software.

scholarly journals Area and Power Efficient Fused Floating-point Dot Product Unit based on Radix-2r Multiplier & Pipeline Feedforward-Cutset-Free Carry-Lookahead Adder

2021 ◽  
Vol 9 (2) ◽  
pp. 782-788
Author(s):  
M. Madhu Babu, K. Rama Naidu
Keyword(s):  
Power Consumption ◽  
Execution Time ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Dot Product ◽  
Power Delay Product ◽  
Dsp Applications ◽  
Standard Library

Fused floating point operations play a major role in many DSP applications to reduce operational area & power consumption. Radix-2r multiplier (using 7-bit encoder technique) & pipeline feedforward-cutset-free carry-lookahead  adder(PFCF-CLA) are used to enhance the traditional FDP unit. Pipeline concept is also infused into system to get the desired pipeline fused floating-point dot product (PFFDP) operations. Synthesis results are obtained using 60nm standard library with 1GHz clock. Power consumption of single & double precision operations are 2.24mW & 3.67mW respectively. The die areas are 27.48 mm2 , 46.72mm2 with an execution time of 1.91 ns , 2.07 ns for a single & double precision operations respectively. Comparison with previous data has also been performed. The area-delay product(ADP) & power-delay product(PDP) of our proposed architecture are 18%,22% & 27%,18% for single and double precision operations respectively.

scholarly journals Accelerating Spike-by-Spike Neural Networks on FPGA with Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Yarib Nevarez ◽  
David Rotermund ◽  
Klaus R. Pawelzik ◽  
Alberto Garcia-Ortiz
Keyword(s):  
Neural Networks ◽  
Floating Point ◽  
Dot Product

scholarly journals Complex signal processing in synthetic gene circuits using cooperative regulatory assemblies

Science ◽  
2019 ◽  
Vol 364 (6440) ◽  
pp. 593-597 ◽  
Author(s):  
Caleb J. Bashor ◽  
Nikit Patel ◽  
Sandeep Choubey ◽  
Ali Beyzavi ◽  
Jané Kondev ◽  
...  
Keyword(s):  
Signal Processing ◽  
Self Assembly ◽  
Design Principle ◽  
Complex Signal ◽  
Synthetic Gene Circuits ◽  
Cellular Decision Making ◽  
Eukaryotic Genes ◽  
Transcription Factor Complexes ◽  
Dynamic Filtering ◽  
Cooperative Assembly

Eukaryotic genes are regulated by multivalent transcription factor complexes. Through cooperative self-assembly, these complexes perform nonlinear regulatory operations involved in cellular decision-making and signal processing. In this study, we apply this design principle to synthetic networks, testing whether engineered cooperative assemblies can program nonlinear gene circuit behavior in yeast. Using a model-guided approach, we show that specifying the strength and number of assembly subunits enables predictive tuning between linear and nonlinear regulatory responses for single- and multi-input circuits. We demonstrate that assemblies can be adjusted to control circuit dynamics. We harness this capability to engineer circuits that perform dynamic filtering, enabling frequency-dependent decoding in cell populations. Programmable cooperative assembly provides a versatile way to tune the nonlinearity of network connections, markedly expanding the engineerable behaviors available to synthetic circuits.

Analog / Mixed-Signal / RF Circuits for Complex Signal Processing

2019 ◽  
Author(s):  
Haruo Kobayashi ◽  
Nene Kushita ◽  
Minh Tri Tran ◽  
Koji Asami ◽  
Hao San ◽  
...  
Keyword(s):  
Signal Processing ◽  
Rf Circuits ◽  
Complex Signal ◽  
Mixed Signal
Sign in / Sign up

Export Citation Format

Share Document