Ambipolar Current Suppression, Analog/RF and Linearity Performance Improvement of Dual Material Stacked Gate Oxide TFET with Dielectric Pocket

In this article, the impact of high-K and low-K dielectric pockets on DC, analog/RF, and linearity performance parameters of dual material stacked gate oxide-dielectric pocket-tunnel field-effect transistor (DMSGO-DP-TFET) is investigated. In this regard, a stacked gate oxide (SiO2 + HfO2) with workfunction engineering is taken into consideration to improve the ON-state current (ION ), and suppress the ambipolar current (Iamb). To further improve the performance of the device, a high-K dielectric pocket (HfO2) is used at the drain-channel interface to suppress the Iamb, and at the source-channel interface a low-K dielectric pocket is used to improve the ION and analog/RF performance. Moreover, length of stacked gate segments (L1, L2, L3), pocket height, and thickness are optimized to attain better ION /IOFF ratio, and suppress the Iamb which helps to achieve higher gain and design of analog/RF circuits. The DMSGO-DP-TFET outperforms the dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide and shows increment in ION /IOFF (∼ 4.23 times), 84 % increment in transconductance (gm), 136 % increment in cut-off frequency (fT ), 126 % increment in gain-bandwidth-product (GBP), and better linearity performance parametrs such as gm2 ,gm3, VIP2, VIP3 and IIP3 making the proposed device useful for low power and radio frequency applications.

A MEMS Tunable Capacitor With Dual Deformation Modes and High Tunability and Linearity

MEMS tunable capacitors have applications in tunable filters and RF circuits where high tunability and Q-factor are desired. Conventional parallel-plate tunable capacitors have a highly nonlinear capacitance-voltage (C-V) response and limited tunability of up to 50% due to fundamental limitation and structural instability. In this work, we present a novel design idea for a parallel-plate tunable capacitor that increases the tuning ratio and provides a smoother (more linear) response. The design uses two modes of deformation, rigid-body displacement of a curved moving electrode before pull-in and deforming the plate after pull-in, and exploits nonlinear structural stiffness to improve the linearity (and the tunability) of the tunable parallel-plate capacitor. The capacitor structure is designed such that when actuation voltage is applied, first the beams holding the moving electrode deform, and capacitance increase similar to conventional design up to pull-in. After the pull-in, the top electrode (which has a curved geometry) is deformed and further increases the capacitance, as the voltage increases. The design may provide an overall simulated tunability of more than 380%, and also has a more linear C-V response. The design is modeled and simulated using ANSYS coupled-field multiphysics solver and the effect of different design parameters are investigated. The simulation results show much high tunability and better linearity than conventional parallel-plate capacitors.

A Monopole Antenna at Quad Band Frequency for Indoor Application

In this paper we concentrate on design of multiband antenna for existing wireless services. At present, the available techniques are modifying the main radiator (bending, folding, meandering and wrapping) which affects the size of antenna. This makes it more complex in implementing on RF circuits. To achieve multiband capability along with compactness in size we go with slotted multiband planar system. Here we design antenna in such a way in works on quad band frequency i.e., GPS, WiMax and WLAN(IEEE 802.11 a,b) for indoor application.

Study of Analog/Rf and Stability Investigation of Surrounded Gate Junctionless Graded Channel MOSFET(SJLGC MOSFET)

This paper explores the potential advantage of surrounded gate junctionless graded channel (SJLGC) MOSFET in the view of its Analog, RF performances using ATLAS TCAD device simulator. The impact of graded channel in the lateral direction on the potential, electric field, and velocity of carriers, energy band along the channel is investigated systematically. The present work mainly emphasises on the superior performance of SJLGC MOSFET by showing higher drain current (ID) , transconductance (gm) ,cut off frequency (fT) , maximum frequency of oscillation (fmax) , critical frequency (fK) .The drain current is improved by 10.03 % in SJLGC MOSFET due to the impact of grading the channel. There is an improvement in fT, fmax, fK by 45%, 29% and 18% respectively in SJLGC MOSFET showing better RF Performance. The dominance of the SJLGC MOSFET over SJL MOSFET is further elucidated by showing 74% improvement in intrinsic voltage gain (gm / gds) indicating its better applications in sub threshold region. But the transconductance generation factor of SJLGC MOSFET is less than SJL MOSFET in the subthreshold region. The intrinsic gate delay (ζD) of SJLGC MOSFET is less in comparison to SJL MOSFET due to the impact of lower gate to gate capacitance (CGG) suggesting better digital switching applications. The simulation results reveal that SJLGC MOSFET can be a competitive contender for the coming generation of RF circuits covering a broad range of operating frequencies in RF spectrum.