To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.
A New Data Transmission Method with Low System Overhead Based on Multiple TSV Sub-Arrays