Abstract
Narrowing design and manufacturing process margins with technology scaling are one of the causes for a reduction in IC chip test margin. This situation is further aggravated by the extensive use of third-party design blocks in contemporary system-on-chips which complicates chip timing constraint. Since a thorough timing verification prior to silicon fabrication is usually not done due to aggressive product launch schedules and escalating design cost, occasionally, a post-silicon timing optimization process is required to eliminate false fails encountered on ATE. An iterative two-dimensional shmoo plots and pin margin analysis are custom optimization methods to accomplish this. However, these methods neglect the interdependencies between different IO timing edges such that a truly optimized condition cannot be attained. In this paper, we present a robust and automated solution based on a genetic algorithm approach. Elimination of shmoo holes and widening of test margins (up to 2x enhancements) are demonstrated on actual product test cases. Besides test margin optimization, this method also offers insights into the criticality of test pins to accelerate failure debug turnaround time.
OPT-VCG: A Novel Proposal for 3D SoC Test Optimization
