Dual bit control low power dynamic content addressable memory design for IoT applications

TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES ◽

10.3906/elk-1907-71 ◽

2021 ◽

Keyword(s):

Low Power ◽

Power Dynamic ◽

Content Addressable Memory ◽

Memory Design ◽

Iot Applications ◽

Dynamic Content

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Low-power content addressable memory design using two-layer P-N match-line control and sensing

Integration ◽

10.1016/j.vlsi.2020.06.001 ◽

2020 ◽

Vol 75 ◽

pp. 73-84

Author(s):

Sheikh Wasmir Hussain ◽

Telajala Venkata Mahendra ◽

Sandeep Mishra ◽

Anup Dandapat

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Memory Design ◽

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Low-power content-addressable memory design using a double match-line (DML) architecture

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2013.6674676 ◽

2013 ◽

Author(s):

Ya-Chun Lin ◽

Yen-Jen Chang ◽

Tung-Chi Wu

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Memory Design ◽

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Static divided word matching line for low-power Content Addressable Memory design

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1329350 ◽

2004 ◽

Author(s):

Kuo-Hsing Cheng ◽

Chia-Hung Wei ◽

Shu-Yu Jiang

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Memory Design ◽

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A Novel High-Density and Low-Power Ternary Content Addressable Memory Design Based on 3D NAND Flash

2020 IEEE Silicon Nanoelectronics Workshop (SNW) ◽

10.1109/snw50361.2020.9131657 ◽

2020 ◽

Author(s):

H. Z. Yang ◽

P. Huang ◽

R. Z. Han ◽

Y. C. Xiang ◽

Y. Feng ◽

...

Keyword(s):

Low Power ◽

High Density ◽

Content Addressable Memory ◽

Memory Design ◽

Ternary Content Addressable Memory

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Low Power and Low Latency Memristive-Ternary Content Addressable Memory Design Using Absolute Path Search Optimization (APSO) Algorithm

International Journal of Psychosocial Rehabilitation ◽

10.37200/ijpr/v23i3/pr190498 ◽

2019 ◽

Vol 23 (3) ◽

pp. 979-986

Author(s):

Dr. Sharmilee K.

Keyword(s):

Low Power ◽

Low Latency ◽

Content Addressable Memory ◽

Memory Design ◽

Ternary Content Addressable Memory ◽

Search Optimization ◽

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Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2008.916624 ◽

2008 ◽

Vol 55 (6) ◽

pp. 1485-1494 ◽

Author(s):

S. Baeg

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Memory Design ◽

Ternary Content Addressable Memory

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Low power high speed Ternary Content Addressable Memory design using 8 MOSFETs and 4 memristors - hybrid structure

8th International Conference on Electrical and Computer Engineering ◽

10.1109/icece.2014.7026989 ◽

2014 ◽

Author(s):

Shawana Tabassum ◽

Farhana Parveen ◽

A.B.M. Harun-ur Rashid

Keyword(s):

Low Power ◽

Hybrid Structure ◽

Content Addressable Memory ◽

Memory Design ◽

Ternary Content Addressable Memory

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Low power FinFET content addressable memory design for 5G communication networks

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2018.03.002 ◽

2018 ◽

Vol 72 ◽

pp. 606-613 ◽

Author(s):

M. Arulvani ◽

M. Mohamed Ismail

Keyword(s):

Low Power ◽

Communication Networks ◽

Content Addressable Memory ◽

Memory Design ◽

5G Communication

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A Low Power Content Addressable Memory Design for Networking Applications

Proceedings of the Student Research Symposium (SRS'13) ◽

10.3850/978-981-07-7393-9_078 ◽

2013 ◽

Author(s):

Roshan Gurumurthy ◽

N. Rueju ◽

R. Varun

Keyword(s):

Low Power ◽

Content Addressable Memory ◽

Memory Design ◽

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Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2019.106528 ◽

2020 ◽

Vol 81 ◽

pp. 106528

Author(s):

Yen-Jen Chang ◽

Kun-Lin Tsai ◽

Yu-Cheng Cheng ◽

Meng-Rong Lu

Keyword(s):

Low Power ◽

Field Effect ◽

Field Effect Transistor ◽

Content Addressable Memory ◽

Memory Design ◽

Ternary Content Addressable Memory ◽

Effect Transistor

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