Low Power and Low Latency Memristive-Ternary Content Addressable Memory Design Using Absolute Path Search Optimization (APSO) Algorithm

Memory Design ◽

Ternary Content Addressable Memory ◽

Search Optimization ◽

Path Search

A Novel High-Density and Low-Power Ternary Content Addressable Memory Design Based on 3D NAND Flash

2020 IEEE Silicon Nanoelectronics Workshop (SNW) ◽

10.1109/snw50361.2020.9131657 ◽

2020 ◽

Author(s):

H. Z. Yang ◽

P. Huang ◽

R. Z. Han ◽

Y. C. Xiang ◽

Y. Feng ◽

...

Keyword(s):

Low Power ◽

High Density ◽

Nand Flash ◽

Memory Design ◽

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2008.916624 ◽

2008 ◽

Vol 55 (6) ◽

pp. 1485-1494 ◽

Cited By ~ 56

Author(s):

S. Baeg

Keyword(s):

Low Power ◽

Memory Design ◽

Low power high speed Ternary Content Addressable Memory design using 8 MOSFETs and 4 memristors - hybrid structure

8th International Conference on Electrical and Computer Engineering ◽

10.1109/icece.2014.7026989 ◽

2014 ◽

Cited By ~ 5

Author(s):

Shawana Tabassum ◽

Farhana Parveen ◽

A.B.M. Harun-ur Rashid

Keyword(s):

Low Power ◽

High Speed ◽

Hybrid Structure ◽

Memory Design ◽

Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment

Computers & Electrical Engineering ◽

10.1016/j.compeleceng.2019.106528 ◽

2020 ◽

Vol 81 ◽

pp. 106528

Author(s):

Yen-Jen Chang ◽

Kun-Lin Tsai ◽

Yu-Cheng Cheng ◽

Meng-Rong Lu

Keyword(s):

Low Power ◽

Field Effect ◽

Field Effect Transistor ◽

Memory Design ◽

Ternary Content Addressable Memory ◽

Effect Transistor

A Novel High-Density and Low-Power Ternary Content Addressable Memory Design Based on 3D NAND Flash

2020 IEEE Silicon Nanoelectronics Workshop (SNW) ◽

10.1109/snw50361.2020.9131662 ◽

2020 ◽

Author(s):

H. Z. Yang ◽

P. Huang ◽

R. Z. Han ◽

Y. C. Xiang ◽

Y. Feng ◽

...

Keyword(s):

Low Power ◽

High Density ◽

Nand Flash ◽

Memory Design ◽

Low power high speed ternary content addressable memory design using MOSFET and memristors

2014 International Conference on Electronics and Communication Systems (ICECS) ◽

10.1109/ecs.2014.6892672 ◽

2014 ◽

Cited By ~ 3

Author(s):

Shawana Tabassum ◽

Farhana Parveen ◽

A. B. M. Harun-ur Rashid

Keyword(s):

Low Power ◽

High Speed ◽

Memory Design ◽

Design and Implementation of a Low Power Ternary Content Addressable Memory (TCAM)

2020 International SoC Design Conference (ISOCC) ◽

10.1109/isocc50952.2020.9333092 ◽

2020 ◽

Author(s):

Karthik S ◽

Karthick D ◽

Sanjaya M V ◽

Madhav Rao

Keyword(s):

Low Power ◽

Design And Implementation ◽

Low-power content addressable memory design using two-layer P-N match-line control and sensing

Integration ◽

10.1016/j.vlsi.2020.06.001 ◽

2020 ◽

Vol 75 ◽

pp. 73-84

Author(s):

Sheikh Wasmir Hussain ◽

Telajala Venkata Mahendra ◽

Sandeep Mishra ◽

Anup Dandapat

Keyword(s):

Low Power ◽

Memory Design ◽

Power Content

2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) ◽

Design of Magnetic Tunnel Junction based Low Power Non-Volatile Ternary Content Addressable Memory

10.1109/rteict46194.2019.9016385 ◽

2019 ◽

Author(s):

Amoghraj ◽

Arunkumar P Chavan

Keyword(s):

Low Power ◽

Tunnel Junction ◽

Magnetic Tunnel Junction ◽

Low-power Ternary Content Addressable Memory (TCAM) array for network applications

2009 International Conference on Communications, Circuits and Systems ◽

10.1109/icccas.2009.5250516 ◽

2009 ◽

Cited By ~ 4

Author(s):

Ataur R. Patwary ◽

Bibiche M. Geuskens ◽

Shih-Lien L. Lu

Keyword(s):

Low Power ◽

Network Applications ◽