Evaluating the impact of task migration in multi-processor systems-on-chip

2010 ◽  
Author(s):  
Gabriel Marchesan Almeida ◽  
Sameer Varyani ◽  
Rémi Busseuil ◽  
Gilles Sassatelli ◽  
Pascal Benoit ◽  
...  
Keyword(s):  
Task Migration ◽  
Systems On Chip ◽  
On Chip ◽  
The Impact

Task Migration in Embedded Systems

2013 ◽  
pp. 275-285 ◽  
Author(s):  
Abderrazak Jemai ◽  
Kamel Smiri ◽  
Habib Smei
Keyword(s):  
Embedded Systems ◽  
Performance Estimation ◽  
Design Flow ◽  
Task Migration ◽  
Performance Constraints ◽  
Systems On Chip ◽  
Great Consideration ◽  
Transaction Level ◽  
On Chip ◽  
The Impact

Task migration has a great consideration is MPSoC design and implementation of embedded systems in order to improve performance related to optimizing execution time or reducing energy consumption. Multi-Processor Systems-on-Chip (MPSoC) are now the leading hardware platform featured in embedded systems. This chapter deals with the impact of task migration as an alternative to meet performance constraints in the design flow. The authors explain the different levels of the design process and propose a methodology to master the migration process at transaction level. This methodology uses some open source tools like SDF3 modified to provide performance estimation at transaction level. These results help the designer to choose the best hardware model in replacement of the previous software implementation of the task object of migration. Using the SDF3 tool, the authors model a multimedia application using SDF graphs. Secondly, they target an MPSoC platform. The authors take a performance constraint to achieve 25 frames per second.

A Classification and Evaluation Framework for NoC Mapping Strategies

2016 ◽  
Vol 26 (02) ◽  
pp. 1730001 ◽  
Author(s):  
Toubaline Nesrine ◽  
Bennouar Djamel ◽  
Mahdoum Ali
Keyword(s):  
Network On Chip ◽  
Evaluation Framework ◽  
Challenging Problem ◽  
Chip Design ◽  
Networks On Chip ◽  
Systems On Chip ◽  
Target Architecture ◽  
On Chip ◽  
The Moment ◽  
The Impact

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.

scholarly journals Modeling of temperature scenarios in a multicore processor system

2013 ◽  
Vol 11 ◽  
pp. 219-225 ◽  
Author(s):  
E. Glocker ◽  
D. Schmitt-Landsiedel
Keyword(s):  
Hot Spot ◽  
Life Time ◽  
Case Scenario ◽  
Worst Case ◽  
Local Fluctuations ◽  
Systems On Chip ◽  
System Temperature ◽  
Multicore System ◽  
On Chip ◽  
The Impact

Abstract. In modern CMOS integrated Systems-on-Chip global temperature variations arise as well as local fluctuations in regions of high activity, resulting in the arise of local hot spots. This in turn can greatly affect reliability and life-time of a chip. Economically affordable processor packaging cannot be provided for the worst case hot spot scenario. In a multicore system a reciprocal influence between the temperatures of neighbouring cores occur leading to increasing core temperature compared to a single core. This results in the need to monitor and regulate the operating temperature during runtime in order to keep it at tolerable values. This can be done in an easy way in an invasive architecture. In this paper the temperature distributions of cores in a multicore system are simulated for various scenarios. Different task allocation techniques and application characteristics as well as different physical conditions such as package types, material parameters and cooling all result in different system power scenarios. The impact of different scenarios which affect the system temperature scenario is investigated. The results are analysed and compared to determine the worst case scenario. With regard to simulation results and practicability the best temperature levelling measures are chosen.

Effective Memory Architectures of Multi-Processor Systems-on-Chip

2010 ◽  
Vol 3 (3) ◽  
pp. 218-231
Author(s):  
Ni Zhou ◽  
Fei Qiao ◽  
Huazhong Yang ◽  
Hui Wang
Keyword(s):  
Systems On Chip ◽  
On Chip ◽  
Memory Architectures

МЕТОДЫ ДОСТИЖЕНИЯ МАКСИМАЛЬНОЙ ЭФФЕКТИВНОСТИ ПЛАТФОРМЫ ПРОТОТИПИРОВАНИЯ ВЫСОКОПРОИЗВОДИТЕЛЬНЫХ СИСТЕМ НА КРИСТАЛЛЕ НА ЗАДАЧАХ ИСКУССТВЕННОГО ИНТЕЛЛЕКТА

2020 ◽  
Vol 96 (3s) ◽  
pp. 585-588
Author(s):  
С.Е. Фролова ◽  
Е.С. Янакова
Keyword(s):  
Neural Network ◽  
Artificial Intelligence ◽  
Computer Vision ◽  
High Performance ◽  
Systems On Chip ◽  
High Performance Systems ◽  
On Chip ◽  
Network Technologies ◽  
Neural Network Technologies

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

Sign in / Sign up

Export Citation Format

Share Document