scholarly journals In-channel misrouting suppression technique for deflection-routed networks on chip

2016 ◽  
Vol 29 (2) ◽  
pp. 309-323
Author(s):  
Igor Stojanovic ◽  
Goran Djordjevic
Keyword(s):  
Large Scale ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Area Efficiency ◽  
Network Load ◽  
Suppression Technique ◽  
Suppression Mechanism ◽  
On Chip ◽  
Large Scale Networks ◽  
The Cost

Deflection routing, where port-contentions in routers are resolved by intentionally misrouting some of packets along unwanted directions instead of storing them, has been proposed as a promising approach for improving power and area efficiency of large-scale networks on chip (NoCs). However, at high network load, when packets are misrouted more frequently, the cost and energy benefits of this simple routing scheme are offset by the performance degradation. To address this problem, we propose a technique that uses small in-channel buffers to capture some of deflected packets before they take a misrouting hop. The captured packets are then looped-back to the routers where they suffered deflection and routed again. To improve the efficiency of this in-channel misrouting suppression scheme we also slightly modify the routing function of the deflection router by restricting the choice of productive directions for misrouted packets. Evaluations on synthetic traffic patterns show that the proposed misrouting suppression mechanism yields an improvement of 36.2% in network saturation throughput when implemented into the conventional deflection-routed network.

A Scalable Redefined Stochastic Blockmodel

2021 ◽  
Vol 15 (3) ◽  
pp. 1-28
Author(s):  
Xueyan Liu ◽  
Bo Yang ◽  
Hechang Chen ◽  
Katarzyna Musial ◽  
Hongxu Chen ◽  
...  
Keyword(s):  
Large Scale ◽  
Network Science ◽  
Learning Algorithm ◽  
State Of The Art ◽  
Real World Data ◽  
Computational Overhead ◽  
Stochastic Blockmodel ◽  
Np Hard Problem ◽  
Large Scale Networks ◽  
The Cost

Stochastic blockmodel (SBM) is a widely used statistical network representation model, with good interpretability, expressiveness, generalization, and flexibility, which has become prevalent and important in the field of network science over the last years. However, learning an optimal SBM for a given network is an NP-hard problem. This results in significant limitations when it comes to applications of SBMs in large-scale networks, because of the significant computational overhead of existing SBM models, as well as their learning methods. Reducing the cost of SBM learning and making it scalable for handling large-scale networks, while maintaining the good theoretical properties of SBM, remains an unresolved problem. In this work, we address this challenging task from a novel perspective of model redefinition. We propose a novel redefined SBM with Poisson distribution and its block-wise learning algorithm that can efficiently analyse large-scale networks. Extensive validation conducted on both artificial and real-world data shows that our proposed method significantly outperforms the state-of-the-art methods in terms of a reasonable trade-off between accuracy and scalability. 1

Performance of Gaussian and Non-Gaussian Synthetic Traffic on Networks-on-Chip

2017 ◽  
Vol 8 (2) ◽  
pp. 33-42 ◽  
Author(s):  
Amit Chaurasia ◽  
Vivek Kumar Sehgal
Keyword(s):  
Packet Loss ◽  
Marginal Distribution ◽  
Loss Probability ◽  
Multicore Architectures ◽  
Traffic Patterns ◽  
Networks On Chip ◽  
Real Time Traffic ◽  
Link Utilization ◽  
On Chip ◽  
Non Gaussian

In this paper, we have worked on the bursty synthetic traffic for Gaussian and Non-Gaussian traffic traces on the NoC architecture. This is the first study on the performance of Gaussian and Non-Gaussian application traffic on the multicore architectures. The real-time traffic having the marginal distribution are Non-Gaussian in nature, so any analytical studies or simulations will not be accurate, and does not capture the true characteristics of application traffic. Simulation is performed on synthetic generated traces for Gaussian and Non-Gaussian traffic for different traffic patterns. The performance of the two traffics is validated by simulating the parameters of packet loss-probability, average link-utilization & average end-to-end latency shows that the Non-Gaussian traffic captures the burstiness more effectively as compared to the Gaussian traffic for the desired application.

Performance Analysis of Temperature Management Approaches in Networks-on-Chip

2012 ◽  
Vol 3 (4) ◽  
pp. 19-41
Author(s):  
Tim Wegner ◽  
Martin Gag ◽  
Dirk Timmermann
Keyword(s):  
Thermal Management ◽  
System Performance ◽  
Large Scale ◽  
Negative Impact ◽  
Temperature Management ◽  
Systematic Analysis ◽  
Networks On Chip ◽  
Chip Temperature ◽  
System Integrity ◽  
On Chip

With the progress of deep submicron technology, power consumption and temperature related issues have become dominant factors for chip design. Therefore, very large-scale integrated systems like Systems-on-Chip (SoCs) are exposed to an increasing thermal stress. On the one hand, this necessitates effective mechanisms for thermal management. On the other hand, application of thermal management is accompanied by disturbance of system integrity and degradation of system performance. In this paper the authors propose to precompute and proactively manage on-chip temperature of systems based on Networks-on-Chip (NoCs). Thereby, traditional reactive approaches, utilizing the NoC infrastructure to perform thermal management, can be replaced. This results not only in shorter response times for application of management measures and a reduction of temperature and thermal imbalances, but also in less impairment of system integrity and performance. The systematic analysis of simulations conducted for NoC sizes ranging from 2x2 to 4x4 proves that under certain conditions the proactive approach is able to mitigate the negative impact of thermal management on system performance while still improving the on-chip temperature profile.

scholarly journals An Effective Algorithm to Find a Cost Minimizing Gateway Deployment for Node-Replaceable Wireless Sensor Networks

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1732
Author(s):  
Sun-Ho Choi ◽  
Yoonkyung Jang ◽  
Hyowon Seo ◽  
Bum Il Hong ◽  
Intae Ryoo
Keyword(s):  
Large Scale ◽  
Computation Time ◽  
Sensor Nodes ◽  
Divide And Conquer ◽  
Divide And Conquer Algorithm ◽  
Computational Speed ◽  
Large Scale Networks ◽  
Gateway Deployment ◽  
The Cost ◽  
The Given

In this paper, we present an efficient way to find a gateway deployment for a given sensor network topology. We assume that the expired sensors and gateways can be replaced and the locations of the gateways are chosen among the given sensor nodes. The objective is to find a gateway deployment that minimizes the cost per unit time, which consists of the maintenance and installation costs. The proposed algorithm creates a cost reference and uses it to find the optimal deployment via a divide and conquer algorithm. Comparing all cases is the most reliable way to find the optimal gateway deployment, but this is practically impossible to calculate, since its computation time increases exponentially as the number of nodes increases. The method we propose increases linearly, and so is suitable for large scale networks. Additionally, compared to stochastic algorithms such as the genetic algorithm, this methodology has advantages in computational speed and accuracy for a large number of nodes. We also verify our methodology through several numerical experiments.

Cluster Based Networks-on-Chip

2013 ◽  
Vol 4 (3) ◽  
pp. 25-41
Author(s):  
Khalid Latif ◽  
Amir-Mohammad Rahmani ◽  
Tiberiu Seceleanu ◽  
Hannu Tenhunen
Keyword(s):  
Critical Path ◽  
Network Interface ◽  
Path Delay ◽  
Traffic Patterns ◽  
Hop Count ◽  
Networks On Chip ◽  
Routing Strategy ◽  
Negative Exponential Distribution ◽  
On Chip ◽  
Negative Exponential

Partial Virtual channel Sharing (PVS) architecture has been proposed to enhance the performance of Networks-on-Chip (NoC) based systems. In this paper, the authors present an efficient and reliable Network Interface (NI) assisted routing strategy for NoC using PVS architecture. For this purpose, NoC system is divided into clusters. Each cluster is a group of two nodes comprising Processing Elements (PE), switches, links, etc. Each PE in a cluster can inject data to the network through a router, which is closer to the destination. This helps to reduce the network load by reducing the average hop count of the network. The proposed architecture can recover the PE disconnected from the network due to network level faults by allowing the PE to transmit and receive the packets through the other router in the cluster. 5×6 crossbar is used for the proposed architecture which requires one more 5×1 multiplexer without increasing the critical path delay of the router as compared to the 5×5 crossbar. The proposed router has been simulated for uniform, transpose and negative exponential distribution (NED) traffic patterns. The simulation results show the significant reduction in average packet latency at the expense of negligible area overhead.

An Adaptive Fault-Tolerant and Congestion Controlled Selection Strategy for On-chip Networks

2019 ◽  
Vol 09 ◽  
Author(s):  
Ashima Arora ◽  
Neeraj K Shukla ◽  
Shaloo Kikan
Keyword(s):  
Fault Tolerant ◽  
Selection Strategy ◽  
Transient Faults ◽  
Traffic Patterns ◽  
Feature Size ◽  
Communication Infrastructure ◽  
Networks On Chip ◽  
Measuring Network ◽  
Hardware Faults ◽  
On Chip

Networks on chip are being developed as a communication infrastructure in the design of Multiprocessor SOCs. With the reduction in feature size, transient faults on the links are becoming a major issue on the performance of NOCs. In this paper, two fault-tolerant algorithms are proposed. In the first algorithm, a faulty link tolerant algorithm is designed which by measuring network loads on the links will reduce transient faults and balances the load. To address the effect of hardware faults, fault and congestion controlled algorithm is designed that not only control the congestion, but also the faults on both links and the nodes. The proposed strategies are evaluated on two different synthetic traffic patterns and the results so obtained shows better network and hardware performance of both the routing in comparison with non-fault-tolerant routing.

Does 0.1 Micron = MACH 1?

1995 ◽  
Vol 380 ◽  
Author(s):  
R. Fabian Pease
Keyword(s):  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
Commercial Use ◽  
Optical Projection ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
The Cost ◽  
The Military

ABSTRACTThe drive to increasingly higher density ultra-large-scale-integration (ULSI) (of electronic circuits) is fuelled primarily by cost; on-chip interconnects are far cheaper than the less dense offchip interconnects. At the same time the escalating cost of an IC factory (‘fab’) is making headlines as it goes through $1B and a large part of this escalation is the cost of high performance lithography tools. The lithographic technology to go below 0.1μm will almost certainly be very different from an extension of today's optical projection and the cost of replacing today's technology will be enormous. A second drawback to higher density is the resistance of narrow interconnects. As a result some people have suggested that this situation is analogous to that of airliner speed which increased over a period of thirty years from about 100 mph to close to 600 mph but has not increased in the last 35 years. Still faster speed was technically possible, and hence was pursued by the military, but is uneconomical for most commercial use. Current technology might take us to 0.1μm which will probably be state of the art 10 years hence so technologies for replacing optical lithography e.g. scanned arrays of proximal probes should be researched now. Other challenges include how to achieve useful interconnect networks employing 50 nm features.

Sign in / Sign up

Export Citation Format

Share Document