A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

2013 ◽  
Vol 4 (1) ◽  
pp. 22-41 ◽  
Author(s):  
Antonio Miele ◽  
Christian Pilato ◽  
Donatella Sciuto
Keyword(s):  
System Level ◽  
System Level Design ◽  
Simulation Environment ◽  
Processing Application ◽  
Systems On Chip ◽  
Simulation Based ◽  
Level Design ◽  
On Chip ◽  
Timing Models

The efficient analysis and exploration of mapping solutions of a parallel application on a heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores that may expose reconfigurable features. This paper proposes a system-level design framework based on SystemC simulations for fulfilling this task, featuring (i) an automated flow for the generation of timing models for the hardware cores starting from the application source code, (ii) an enhanced simulation environment for SystemC architectures enabling the specification and modification of mapping choices only by changing an XML descriptor, and (iii) a flexible controller of the simulation environment supporting the exploration of various mapping solutions featuring a customizable engine. The proposed framework has been validated with a case study considering an image processing application to show the possibility to automatically exploring alternative solutions onto a reconfigurable MPSoC platform.

Systemc and OCAPI-XL Based System-Level Design for Reconfigurable Systems-on-Chip

2006 ◽  
pp. 255-269 ◽  
Author(s):  
Kari Tiensyrjä ◽  
Miroslav Cupak ◽  
Kostas Masselos ◽  
Marko Pettissalo ◽  
Konstantinos Potamianos ◽  
...  
Keyword(s):  
System Level ◽  
Reconfigurable Systems ◽  
System Level Design ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

2014 ◽  
pp. 150-179
Author(s):  
Haoyuan Ying ◽  
Klaus Hofmann ◽  
Thomas Hollstein
Keyword(s):  
Embedded Systems ◽  
Design Optimization ◽  
Optimization Methods ◽  
Design Methods ◽  
System Level ◽  
System Level Design ◽  
Level Design ◽  
On Chip ◽  
Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

System-Level Design of NoC-Based Dependable Embedded Systems

2014 ◽  
pp. 478-512
Author(s):  
Mihkel Tagel ◽  
Peeter Ellervee ◽  
Gert Jervan
Keyword(s):  
Design Space Exploration ◽  
System Level ◽  
System Level Design ◽  
Levels Of Abstraction ◽  
Technology Scaling ◽  
Communication Problems ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip ◽  
Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

System-Level Design of NoC-Based Dependable Embedded Systems

2011 ◽  
pp. 1-36 ◽  
Author(s):  
Mihkel Tagel ◽  
Peeter Ellervee ◽  
Gert Jervan
Keyword(s):  
Design Space Exploration ◽  
System Level ◽  
System Level Design ◽  
Levels Of Abstraction ◽  
Technology Scaling ◽  
Communication Problems ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip ◽  
Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

A Case Study of FPGA Blokus Duo Solver by System-Level Design

2014 ◽  
Vol 42 (4) ◽  
pp. 57-62
Author(s):  
Yuki Ando ◽  
Masataka Ogawa ◽  
Yuya Mizoguchi ◽  
Kouta Kumagai ◽  
Miaw Torng-Der ◽  
...  
Keyword(s):  
System Level ◽  
System Level Design ◽  
Level Design

A system-level design methodology for application-specific networks-on-chip

2009 ◽  
Vol 3 (3) ◽  
pp. 167-177 ◽  
Author(s):  
Alexandros Bartzas ◽  
Lazaros Papadopoulos ◽  
Dimitrios Soudris
Keyword(s):  
Design Methodology ◽  
System Level ◽  
System Level Design ◽  
Networks On Chip ◽  
Level Design ◽  
On Chip ◽  
Application Specific
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