System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

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A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/jertcs.2013010102 ◽

2013 ◽

Vol 4 (1) ◽

pp. 22-41 ◽

Cited By ~ 2

Author(s):

Antonio Miele ◽

Christian Pilato ◽

Donatella Sciuto

Keyword(s):

System Level ◽

System Level Design ◽

Simulation Environment ◽

Processing Application ◽

Systems On Chip ◽

Simulation Based ◽

Level Design ◽

On Chip ◽

Timing Models

The efficient analysis and exploration of mapping solutions of a parallel application on a heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) is usually a challenging task in system-level design, in particular when the architecture integrates hardware cores that may expose reconfigurable features. This paper proposes a system-level design framework based on SystemC simulations for fulfilling this task, featuring (i) an automated flow for the generation of timing models for the hardware cores starting from the application source code, (ii) an enhanced simulation environment for SystemC architectures enabling the specification and modification of mapping choices only by changing an XML descriptor, and (iii) a flexible controller of the simulation environment supporting the exploration of various mapping solutions featuring a customizable engine. The proposed framework has been validated with a case study considering an image processing application to show the possibility to automatically exploring alternative solutions onto a reconfigurable MPSoC platform.

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System-Level Design of NoC-Based Dependable Embedded Systems

Design and Test Technology for Dependable Systems-on-Chip - Advances in Computer and Electrical Engineering ◽

10.4018/978-1-60960-212-3.ch001 ◽

2011 ◽

pp. 1-36 ◽

Cited By ~ 3

Author(s):

Mihkel Tagel ◽

Peeter Ellervee ◽

Gert Jervan

Keyword(s):

Design Space Exploration ◽

System Level ◽

System Level Design ◽

Levels Of Abstraction ◽

Technology Scaling ◽

Communication Problems ◽

Systems On Chip ◽

Level Design ◽

On Chip ◽

Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

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Fast system-level design space exploration for low power configurable multimedia systems-on-chip

15th Annual IEEE International ASIC/SOC Conference ◽

10.1109/asic.2002.1158047 ◽

2003 ◽

Cited By ~ 4

Author(s):

F. Polloni ◽

L. Mazzoni ◽

S. Di Matteo

Keyword(s):

Low Power ◽

Design Space Exploration ◽

Design Space ◽

Space Exploration ◽

Multimedia Systems ◽

System Level ◽

System Level Design ◽

Fast System ◽

Systems On Chip ◽

On Chip

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Parallel-Pipelined Video Processing in Multicore Heterogeneous Systems on Chip

Proceedings of Universities ELECTRONICS ◽

10.24151/1561-5405-2021-26-2-172-183 ◽

2021 ◽

Vol 26 (2) ◽

pp. 172-183

Author(s):

E.S. Yanakova ◽

◽

G.T. Macharadze ◽

L.G. Gagarina ◽

A.A. Shvachko ◽

...

Keyword(s):

Video Processing ◽

High Efficiency ◽

Heterogeneous Systems ◽

Video Data ◽

System Level ◽

Video Information ◽

Systems On Chip ◽

The Face ◽

Parallel Pipelined ◽

On Chip

A turn from homogeneous to heterogeneous architectures permits to achieve the advantages of the efficiency, size, weight and power consumption, which is especially important for the built-in solutions. However, the development of the parallel software for heterogeneous computer systems is rather complex task due to the requirements of high efficiency, easy programming and the process of scaling. In the paper the efficiency of parallel-pipelined processing of video information in multiprocessor heterogeneous systems on a chip (SoC) such as DSP, GPU, ISP, VDP, VPU and others, has been investigated. A typical scheme of parallel-pipelined processing of video data using various accelerators has been presented. The scheme of the parallel-pipelined video data on heterogeneous SoC 1892VM248 has been developed. The methods of efficient parallel-pipelined processing of video data in heterogeneous computers (SoC), consisting of the operating system level, programming technologies level and the application level, have been proposed. A comparative analysis of the most common programming technologies, such as OpenCL, OpenMP, MPI, OpenAMP, has been performed. The analysis has shown that depend-ing on the device finite purpose two programming paradigms should be applied: based on OpenCL technology (for built-in system) and MPI technology (for inter-cell and inter processor interaction). The results obtained of the parallel-pipelined processing within the framework of the face recognition have confirmed the effectiveness of the chosen solutions.

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Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch007 ◽

2014 ◽

pp. 150-179

Author(s):

Haoyuan Ying ◽

Klaus Hofmann ◽

Thomas Hollstein

Keyword(s):

Embedded Systems ◽

Design Optimization ◽

Optimization Methods ◽

Design Methods ◽

System Level ◽

System Level Design ◽

Level Design ◽

On Chip ◽

Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

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