An Effective Algorithm for Tool-Path Airtime Optimization during Leather Cutting

2010 ◽  
Vol 102-104 ◽  
pp. 373-377 ◽  
Author(s):  
Wei Bo Yang ◽  
Yan Wei Zhao ◽  
Jing Jie ◽  
Wan Liang Wang
Keyword(s):  
Simulated Annealing ◽  
Tool Path ◽  
Simulated Annealing Algorithm ◽  
Dynamic Programming Algorithm ◽  
Programming Algorithm ◽  
Genetic Simulated Annealing Algorithm ◽  
Generalized Traveling Salesman Problem ◽  
Hybrid Intelligence ◽  
Optimal Contour ◽  
Cutting Path

Tool-path airtime optimization problem during multi-contour processing in leather cutting is regarded as generalized traveling salesman problem. A hybrid intelligence algorithm is proposed. The improved genetic simulated annealing algorithm is applied to optimize cutting path selected arbitrarily firstly, and an optimal contour sequence is founded, then problem is changed into multi- segment map problem solved with dynamic programming algorithm. The algorithm's process and its various parameters are given simultaneously, and its performance is compared with simulated annealing and standard genetic algorithm alone. The results show that the algorithm is more effective.

An Optimized Algorithm of Numerical Cutting-Path Control in Garment Manufacturing

2013 ◽  
Vol 796 ◽  
pp. 454-457 ◽  
Author(s):  
Jing Ye ◽  
Zhi Ge Chen
Keyword(s):  
Dynamic Programming ◽  
Ant Colony Algorithm ◽  
Travelling Salesman Problem ◽  
Dynamic Programming Algorithm ◽  
Ant Colony ◽  
Numerical Control ◽  
Programming Algorithm ◽  
Intelligence Algorithm ◽  
Hybrid Intelligence ◽  
Cutting Path

The garment cutting is a key process during the garment production. Most companies apply the manual labor or simple mechanical aids to achieve the goals. While these methods cost much time and labor. More and more automatic cutting equipment is applied to the garment cutting so as to save time, labor and materials. During the process of cutting, some problems are coming up, especially the cutting path. The cutting path of the garment numerical control cutter is regarded as generalized travelling salesman problem (GTSP). The garment contours can be regarded as the set of cities, and the nodes of a single contour can be regarded as cities. The cutter visits every contour exactly once. A hybrid intelligence algorithm was proposed to solve the problem. The ant colony algorithm was applied to a selected cutting path arbitrarily, an optimal contour sequence was found. Then the garment contour sequences shortest path was transformed into multi-segment graph shortest problem which is solved with the dynamic programming algorithm in order to optimize the knifes in-out point. The final optimal cutting path was constructed with ant colony optimization algorithm and dynamic programming algorithm. The practical application shows that the hybrid intelligence algorithm has satisfactory solution quality.

Optimal scheduling algorithms of system chip power density based on network on chip

2021 ◽  
pp. 120-127
Author(s):  
Jiashen Li ◽  
◽  
Yun Pan ◽  
Keyword(s):  
Dynamic Programming ◽  
Power Density ◽  
Simulated Annealing Algorithm ◽  
Dynamic Programming Algorithm ◽  
Network On Chip ◽  
Thermal Design ◽  
Optimal Scheduling ◽  
Programming Algorithm ◽  
System Throughput ◽  
On Chip

The improvement of chip integration leads to the increase of power density of system chips, which leads to the overheating of system chips. When dispatching the power density of system chips, some working modules are selectively closed to avoid all modules on the chip being turned on at the same time and to solve the problem of overheating. Taking 2D grid-on-chip network as the research object, an optimal scheduling algorithm of system-on-chip power density based on network-on-chip (NoC) is proposed. Under the constraints of thermal design power (TDP) and system, dynamic programming algorithm is used to solve the optimal application set throughput allocation from bottom to top by dynamic programming for the number and frequency level of each application configuration processor under the given application set of network-on-chip. On this basis, the simulated annealing algorithm is used to complete the application mapping aiming at heat dissipation effect and communication delay. The open and closed processor layout is determined. After obtaining the layout results, the TDP is adjusted. The maximum TDP constraint is iteratively searched according to the feedback loop of the system over-hot spots, and the power density scheduling performance of the system chip is maximized under this constraint, so as to ensure the system core. At the same time, chip throughput can effectively solve the problem of chip overheating. The experimental results show that the proposed algorithm increases the system chip throughput by about 11%, improves the system throughput loss, and achieves a balance between the system chip power consumption and scheduling time.

scholarly journals Fault Localization Based on Hybrid Genetic Simulated Annealing Algorithm

2021 ◽  
Vol 28 (2) ◽  
pp. 101-109
Keyword(s):  
Simulated Annealing ◽  
Software Testing ◽  
Simulated Annealing Algorithm ◽  
Search Algorithm ◽  
Fault Localization ◽  
Good Effect ◽  
Test Case ◽  
Genetic Simulated Annealing Algorithm ◽  
Starting Point ◽  
Annealing Algorithm

Software testing is an important stage in the software development process, which is the key to ensure software quality and improve software reliability. Software fault localization is the most important part of software testing. In this paper, the fault localization problem is modeled as a combinatorial optimization problem, using the function call path as a starting point. A heuristic search algorithm based on hybrid genetic simulated annealing algorithm is used to locate software defects. Experimental results show that the fault localization method, which combines genetic algorithm, simulated annealing algorithm and function correlation analysis method, has a good effect on single fault localization and multi-fault localization. It greatly reduces the requirement of test case coverage and the burden of the testers, and improves the effect of fault localization.

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