Test Scheduling Method Based on Cellular Genetic Algorithm for System on Chip

2010 ◽  
Vol 663-665 ◽  
pp. 670-673
Author(s):  
Zhong Liang Pan ◽  
Ling Chen
Keyword(s):  
Genetic Algorithm ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Scheduling Problem ◽  
Good Test ◽  
Cellular Genetic Algorithm ◽  
Scheduling Method ◽  
On Chip ◽  
Feasible Solutions

The main aspects for the test of system on chip (SoC) are designing testability architectures and solving the test scheduling. The test time of SoC can be reduced by using good test scheduling schemes. A test scheduling method based on cellular genetic algorithm is presented in this paper. In the method, the individuals are used to represent the feasible solutions of the test scheduling problem, the individuals are distributed over a grid or connected graph, the genetic operations such as selection and mutation are applied locally in some neighborhood of each individual. The test scheduling schemes are obtained by carrying out the evolutionary operations for the populations. A lot of experiments are performed for the SoC benchmark circuits, the experimental results show that the better test scheduling schemes can be obtained by the method in this paper.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques

2019 ◽  
Vol 32 (9) ◽  
pp. 5303-5312 ◽  
Author(s):  
Gokul Chandrasekaran ◽  
Sakthivel Periyasamy ◽  
Karthikeyan Panjappagounder Rajamanickam
Keyword(s):  
Artificial Intelligence ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
On Chip

A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

2018 ◽  
Vol 17 (02) ◽  
pp. 1850010
Author(s):  
Wissam Marrouche ◽  
Rana Farah ◽  
Haidar M. Harmanani
Keyword(s):  
Evolutionary Algorithm ◽  
System On Chip ◽  
Test Scheduling ◽  
Scheduling Problem ◽  
Single Chip ◽  
Simultaneous Test ◽  
Soc Test ◽  
Strength Pareto Evolutionary Algorithm ◽  
Tightly Coupled ◽  
On Chip

System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

Research of Flexible Dynamic Scheduling Problem Based on Genetic Algorithm

2009 ◽  
Vol 16-19 ◽  
pp. 743-747
Author(s):  
Yu Wu ◽  
Xin Cun Zhuang ◽  
Cong Xin Li
Keyword(s):  
Genetic Algorithm ◽  
Flexible Manufacturing ◽  
Manufacturing Systems ◽  
Dynamic Scheduling ◽  
Scheduling Problem ◽  
Static Scheduling ◽  
Coding Method ◽  
Scheduling Method ◽  
Distribution Principle ◽  
Working Procedure

Solve the flexible dynamic scheduling problem by using “dynamic management & static scheduling” method. Aim at the property of flexible Manufacturing systems, the dynamic scheduling methods are analyzed and a coding method based on working procedure is improved in this paper. Thus it can be efficiently solve the problem of multiple working routes selection under the active distribution principle. On the other hand, the self-adaptive gene is provided and the parameters of the genetic algorithm are defined. In such a solution, the scheduling is confirmed to be simple and efficient.

scholarly journals Measuring Static Parameters of Embedded ADC Core

2011 ◽  
Vol 62 (2) ◽  
pp. 80-86
Author(s):  
Franc Novak ◽  
Peter Mrak ◽  
Anton Biasizzo
Keyword(s):  
Feasibility Study ◽  
Theoretical Background ◽  
System On Chip ◽  
Test Time ◽  
Hardware Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
On Chip ◽  
The Impact ◽  
Minimal Hardware

Measuring Static Parameters of Embedded ADC CoreThe paper presents the results of a feasibility study of measuring static parameters of ADC cores embedded in a System-on-Chip. Histogram based technique is employed because it is suitable for built-in self-test. While the theoretical background of the technique has been covered by numerous papers, less attention has been given to implementations in practice. Our goal was the implementation of histogram test in a IEEE Std 1500 wrapper. Two different solutions pursuing either minimal test time or minimal hardware overhead are described. The impact of MOS switches at ADC input on the performed measurements was considered.

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