scholarly journals All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Xuan Tran
Integration ◽  
2017 ◽  
Vol 57 ◽  
pp. 45-51 ◽  
Author(s):  
Hongmei Chen ◽  
Yunsheng Pan ◽  
Yongsheng Yin ◽  
Fujiang Lin

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.


VLSI Design ◽  
2016 ◽  
Vol 2016 ◽  
pp. 1-8 ◽  
Author(s):  
Hongmei Chen ◽  
Yongsheng Yin ◽  
Honghui Deng ◽  
Fujiang Lin

A low complexity all-digital background calibration technique based on statistics is proposed. The basic idea of the statistics calibration technique is that the output average energy of each channel of TIADC will be consistent ideally, since each channel samples the same input signal, and therefore the energy deviation directly reflects the mismatch errors of channels. In this work, the offset mismatch and gain mismatch are calibrated by an adaptive statistics calibration algorithm based on LMS iteration; the timing mismatch is estimated by performing the correlation calculation of the outputs of subchannels and corrected by an improved fractional delay filter based on Farrow structure. Applied to a four-channel 12-bit 400 MHz TIADC, simulation results show that, with calibration, the SNDR raises from 22.5 dB to 71.8 dB and ENOB rises from 3.4 bits to 11.6 bits for a 164.6 MHz sinusoidal input. Compared with traditional methods, the proposed schemes are more feasible to implement and consume less hardware resources.


Author(s):  
Han Le Duc ◽  
Van-Phuc Hoang ◽  
Duc-Minh Nguyen

This paper presents a fully digital background calibration technique of the gain and timing mismatches in undersampling Time-Interleaved Analog-to-Digital Converters for the wideband bandlimited input signal at any Nyquist bands. The proposed technique does not require an additional reference channel nor a pilot input. The channel mismatch parameters are estimated based on the mismatch frequency band. The experimental results shows the efficiency of the proposed mitigation technique with the SNDR improvement of 16dB for 4-channel 60dB SNR TIADC clocked at 2.7GHz given a multi-tone input occupied at the third Nyquist band. The hardware architecture of the proposed technique is designed and validated on Altera FPGA DE4 board. The synthesized design utilizes a very little amount of the hardware resource in the FPGA chip and works correctly on a Hardware-In-the-Loop emulation framework.


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