Model-Based Design Flow Driven by Integrated Modular Avionic Simulations

2013 ◽  
Author(s):  
Julien Savard ◽  
Lin Bao ◽  
Guy Bois ◽  
Jean-François Boland
Keyword(s):  
Design Flow ◽  
Model Based

Foundation for Model Integration: Semantic Backplane

2012 ◽  
Author(s):  
Gabor Simko ◽  
Tihamer Levendovszky ◽  
Sandeep Neema ◽  
Ethan Jackson ◽  
Ted Bapty ◽  
...  
Keyword(s):  
Design Flow ◽  
Model Transformations ◽  
Model Integration ◽  
Mathematical Framework ◽  
Modeling Languages ◽  
Tool Chain ◽  
Model Based ◽  
Essential Properties ◽  
The Individual ◽  
Term Algebra

One of the primary goals of the Adaptive Vehicle Make (AVM) program of DARPA is the construction of a model-based design flow and tool chain, META, that will provide significant productivity increase in the development of complex cyber-physical systems. In model-based design, modeling languages and their underlying semantics play fundamental role in achieving compositionality. A significant challenge in the META design flow is the heterogeneity of the design space. This challenge is compounded by the need for rapidly evolving the design flow and the suite of modeling languages supporting it. Heterogeneity of models and modeling languages is addressed by the development of a model integration language – CyPhy – supporting constructs needed for modeling the interactions among different modeling domains. CyPhy targets simplicity: only those abstractions are imported from the individual modeling domains to CyPhy that are required for expressing relationships across sub-domains. This “semantic interface” between CyPhy and the modeling domains is formally defined, evolved as needed and verified for essential properties (such as well-formedness and invariance). Due to the need for rapid evolvability, defining semantics for CyPhy is not a “one-shot” activity; updates, revisions and extensions are ongoing and their correctness has significant implications on the overall consistency of the META tool chain. The focus of this paper is the methods and tools used for this purpose: the META Semantic Backplane. The Semantic Backplane is based on a mathematical framework provided by term algebra and logics, incorporates a tool suite for specifying, validating and using formal structural and behavioral semantics of modeling languages, and includes a library of metamodels and specifications of model transformations.

A Model-based Design Flow for Asynchronous Implementations from Synchronous Specifications

2021 ◽  
Author(s):  
Yu Bai ◽  
Omair Rafique ◽  
Klaus Schneider
Keyword(s):  
Design Flow ◽  
Model Based

Model-based design flow for NoC-based MPSoCs

2010 ◽  
Author(s):  
Luciano Ost ◽  
Leandro Soares Indrusiak ◽  
Sanna Maatta ◽  
Marcelo Mandelli ◽  
Jari Nurmi ◽  
...  
Keyword(s):  
Design Flow ◽  
Model Based

scholarly journals BlackBox Model Based VLSI Hierarchical Floorplanning

2019 ◽  
Vol 8 (6) ◽  
pp. 2604-2607
Keyword(s):  
Physical Design ◽  
Design Flow ◽  
Prototype Model ◽  
Asic Design ◽  
Model Based ◽  
Initial Stage ◽  
Floor Planning ◽  
Run Time ◽  
Prototype Design

Nowadays in VLSI number of transistors integrated on a single silicon chip is increasing day by day and the complexity of the design is increases tremendously. This makes very difficult for the designer and EDA tools. As number of instances increases the run time and memory for implementing the design increases. This will make more pressure on the designer because if product is not completed within the time to market company will lost so much of money. Floorplanning is the basic building step for any hierarchical physical design flow. Floorplanning is taking more amount of time in entire design hierarchical flow. If floorplanning is not good the entire design will take more time and it will increase a greater number of iterations to complete the design. In the top-level chip planning the quality of the floorplanning depends on the proper alignment of blocks and easy to meet the timing and congestion. To reduce memory size of CPU and run time, in this project we are using a method of Backbox model based top level hierarchical floorplanning based physical design. The main aim of this project is to reduce the number of instances which are not necessary in the top level chip floor planning which reduces peak memory for the design and also reducing CPU run time for getting proper prototype design in the top level ASIC design and estimate the congestion in the design at initial stage and modify floor planning to obtain quality of prototype model in the floorplanning. This project is designed on cadence encounter tool.

scholarly journals Model-based implementation of self-configurable intellectual property modules for image histogram calculation in FPGAs

2017 ◽  
Vol 37 (2) ◽  
pp. 74-81
Author(s):  
Luis Manuel Garcés Socarrás ◽  
Daniel Alejandro Romero Ares ◽  
Alejandro José Cabrera Sarmiento ◽  
Santiago Sánchez Solano ◽  
Piedad Brox Jiménez
Keyword(s):  
Intellectual Property ◽  
Design Flow ◽  
Design Technique ◽  
System Generator ◽  
Image Histogram ◽  
Model Based ◽  
Application Requirements ◽  
Xilinx Fpga ◽  
Processing Flow ◽  
Ip Module

This work presents the development of self-modifiable Intellectual Property (IP) modules for histogram calculation using the modelbased design technique provided by Xilinx System Generator. In this work, an analysis and a comparison among histogram calculation architectures are presented, selecting the best solution for the design flow used. Also, the paper emphasizes the use of generic architectures capable of been adjustable by a self configurable procedure to ensure a processing flow adequate to the application requirements. In addition, the implementation of a configurable IP module for histogram calculation using a model-based design flow is described and some implementation results are shown over a Xilinx FPGA Spartan-6 LX45.

Actor-Oriented Design of Embedded Hardware and Software Systems

2003 ◽  
Vol 12 (03) ◽  
pp. 231-260 ◽  
Author(s):  
Edward A. Lee ◽  
Stephen Neuendorffer ◽  
Michael J. Wirthlin
Keyword(s):  
Design Flow ◽  
Software Systems ◽  
Multiple Models ◽  
Instruction Set ◽  
Problem Domain ◽  
Models Of Computation ◽  
Abstraction Layer ◽  
Model Based ◽  
Constrained Models ◽  
Platform Based Design

In this paper, we argue that model-based design and platform-based design are two views of the same thing. A platform is an abstraction layer in the design flow. For example, a core-based architecture and an instruction set architecture are platforms. We focus on the set of designs induced by this abstraction layer. For example, the set of all ASICs based on a particular core-based architecture and the set of all x86 programs are induced sets. Hence, a platform is equivalently a set of designs. Model-based design is about using platforms with useful modeling properties to specify designs, and then synthesizing implementations from these specifications. Hence model-based design is the view from above (more abstract, closer to the problem domain) and platform-based design is the view from below (less abstract, closer to the implementation technology). One way to define a platform is to provide a design language. Any valid expression in the language is an element of the set. A platform provides a set of constraints together with known tradeoffs that flow from those constraints. Actor-oriented platforms, such as Simulink, abstract aspects of program-level platforms, such as Java, C++, and VHDL. Actor-oriented platforms orthogonalize the actor definition language and the actor composition language, enabling highly polymorphic actor definitions and design using multiple models of computation. In particular, we concentrate on the use of constrained models of computation in design. The modeling properties implied by well chosen constraints allow more easily understood designs and are preserved during synthesis into program-level descriptions. We illustrate these concepts by describing a design framework built on Ptolemy II.

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