Automatic Formal Verification of SysML State Machine Diagrams for Vehicular Control Systems

2021 ◽  
Author(s):  
Maziar Mahani ◽  
Denise Rizzo ◽  
Chris Paredis ◽  
Yue Wang
Keyword(s):  
Formal Verification ◽  
Control Systems ◽  
State Machine

Formal Verification of a Subset of UML Diagrams

2011 ◽  
pp. 14-24
Author(s):  
Allaoua Chaoui ◽  
Okba Tibermacine ◽  
Amer R. Zerek
Keyword(s):  
Formal Verification ◽  
Programming Language ◽  
Formal Specification ◽  
State Machine ◽  
Declarative Programming ◽  
Sequence Diagrams ◽  
Uml Diagrams ◽  
Approach Goals ◽  
Formal Specification Language ◽  
State Machine Diagram

We introduce an approach that deals with the verification of UML collaboration and sequence diagrams in respect to the objects internal behaviors which are commonly represented by state machine diagrams. The approach is based on the translation of theses diagrams to Maude specifications. In fact, Maude is a declarative programming language, an executable formal specification language, and also a formal verification system, which permit the achievement of the approach goals. We define in details the rules of translating UML diagrams elements into their corresponding Maude specifications. We present the algebraic structures that represent the OR-States and the AND-states in a state machine diagram, and the structure that represents the collaboration and the sequence diagrams. Also, we explain the mechanism of the execution and the verification of the translated specification, which is based on rewriting logics rules.

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